Lines Matching +full:0 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
5 #define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */
6 #define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */
7 #define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */
8 #define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */
9 #define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */
10 #define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */
11 #define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */
12 #define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */
13 #define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */
14 #define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */
15 #define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR …
17 #define I40E_PFPE_CQPTAIL 0x00008080 /* Reset: PFR */
19 #define I40E_PFPE_CQPDB 0x00008000 /* Reset: PFR */
20 #define I40E_PFPE_CCQPSTATUS 0x00008100 /* Reset: PFR */
21 #define I40E_PFPE_CCQPHIGH 0x00008200 /* Reset: PFR */
22 #define I40E_PFPE_CCQPLOW 0x00008180 /* Reset: PFR */
23 #define I40E_PFPE_CQARM 0x00131080 /* Reset: PFR */
24 #define I40E_PFPE_CQACK 0x00131100 /* Reset: PFR */
25 #define I40E_PFPE_AEQALLOC 0x00131180 /* Reset: PFR */
26 #define I40E_PFPE_CQPERRCODES 0x00008880 /* Reset: PFR */
27 #define I40E_PFPE_WQEALLOC 0x00138C00 /* Reset: PFR */
28 #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */
29 #define I40E_GLPE_CPUSTATUS0 0x0000D040 /* Reset: PE_CORER */
30 #define I40E_GLPE_CPUSTATUS1 0x0000D044 /* Reset: PE_CORER */
31 #define I40E_GLPE_CPUSTATUS2 0x0000D048 /* Reset: PE_CORER */
32 #define I40E_GLPE_CRITERR 0x000B4000 /* Reset: PE_CORER */
33 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */
34 #define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
35 #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR …
36 #define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */
38 #define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
39 #define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
40 #define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
41 #define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
42 #define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
44 #define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
45 #define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
46 #define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
47 #define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
48 #define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
49 #define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
51 #define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
52 #define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
53 #define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
54 #define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
55 #define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
56 #define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
57 #define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
58 #define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
59 #define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
60 #define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
61 #define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
62 #define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
63 #define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
64 #define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
65 #define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
66 #define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
67 #define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
68 #define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
69 #define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
70 #define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
71 #define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
72 #define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
73 #define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
74 #define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
75 #define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
76 #define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
77 #define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
78 #define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
79 #define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
80 #define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
81 #define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
83 #define I40IW_DB_ADDR_OFFSET (4 * 1024 * 1024 - 64 * 1024)
87 #define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Rese…
89 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX GENMASK(10, 0)
92 #define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset:…
96 #define I40E_PFINT_CEQCTL_MSIX_INDX_S 0
97 #define I40E_PFINT_CEQCTL_MSIX_INDX GENMASK(7, 0)
101 #define I40E_PFINT_CEQCTL_MSIX0_INDX GENMASK(15, 13)
112 #define I40E_PFPE_CCQPSTATUS_CCQP_DONE_S 0
113 #define I40E_PFPE_CCQPSTATUS_CCQP_DONE BIT_ULL(0)
118 #define I40E_PFINT_DYN_CTLN_INTENA_S 0
119 #define I40E_PFINT_DYN_CTLN_INTENA BIT(0)
122 #define I40E_CQPSQ_CQ_CQID_S 0
123 #define I40E_CQPSQ_CQ_CQID GENMASK_ULL(15, 0)
124 #define I40E_COMMIT_FPM_CQCNT_S 0
125 #define I40E_COMMIT_FPM_CQCNT GENMASK_ULL(17, 0)
127 #define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4))
132 I40IW_MAX_PUSH_PAGE_COUNT = 0,
154 #define I40IW_MAX_QP_WRS ((I40IW_QP_SW_MAX_SQ_QUANTA - IRDMA_SQ_RSVD) / I40IW_MAX_QUANTA_PER_WR)
157 #define NULL_QUEUE_INDEX 0x7FF