Lines Matching +full:precondition +full:- +full:timeout
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015-2018 Intel Corporation.
38 int flush = 0; /* re-read sendctrl to make sure it is flushed */ in pio_send_control()
41 spin_lock_irqsave(&dd->sendctrl_lock, flags); in pio_send_control()
50 for (i = 0; i < ARRAY_SIZE(dd->vld); i++) in pio_send_control()
51 if (!dd->vld[i].mtu) in pio_send_control()
86 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in pio_send_control()
93 #define SCS_POOL_0 -1
94 #define SCS_POOL_1 -2
97 #define SCC_PER_VL -1
98 #define SCC_PER_CPU -2
99 #define SCC_PER_KRCVQ -3
131 { 10000, -1 }, /* pool 0 */
132 { 0, -1 }, /* pool 1 */
138 * 100th of 1% of memory to use, -1 if blocks
148 * start at -1 and increase negatively. Map them as:
149 * -1 => 0
150 * -2 => 1
153 * Return -1 on non-wildcard input, otherwise convert to a pool number.
158 return -1; /* non-wildcard */ in wildcard_to_pool()
159 return -wc - 1; in wildcard_to_pool()
184 int total_blocks = (chip_pio_mem_size(dd) / PIO_BLOCK_SIZE) - 1; in init_sc_pools_and_sizes()
197 * setting it to a fixed size. The allocation allows 3-deep buffering in init_sc_pools_and_sizes()
212 * - copy the centipercents/absolute sizes from the pool config in init_sc_pools_and_sizes()
213 * - sanity check these values in init_sc_pools_and_sizes()
214 * - add up centipercents, then later check for full value in init_sc_pools_and_sizes()
215 * - add up absolute blocks, then later check for over-commit in init_sc_pools_and_sizes()
236 return -EINVAL; in init_sc_pools_and_sizes()
248 return -EINVAL; in init_sc_pools_and_sizes()
257 return -EINVAL; in init_sc_pools_and_sizes()
266 return -EINVAL; in init_sc_pools_and_sizes()
271 * - copy from the context size config in init_sc_pools_and_sizes()
272 * - replace context type wildcard counts with real values in init_sc_pools_and_sizes()
273 * - add up non-memory pool block sizes in init_sc_pools_and_sizes()
274 * - add up memory pool user counts in init_sc_pools_and_sizes()
289 count = dd->n_krcv_queues; in init_sc_pools_and_sizes()
293 count = dd->num_rcv_contexts - dd->n_krcv_queues; in init_sc_pools_and_sizes()
299 return -EINVAL; in init_sc_pools_and_sizes()
302 count = chip_send_contexts(dd) - total_contexts; in init_sc_pools_and_sizes()
308 * number or -1 if a fixed (non-negative) value. The fixed in init_sc_pools_and_sizes()
313 if (pool == -1) { /* non-wildcard */ in init_sc_pools_and_sizes()
322 return -EINVAL; in init_sc_pools_and_sizes()
325 dd->sc_sizes[i].count = count; in init_sc_pools_and_sizes()
326 dd->sc_sizes[i].size = size; in init_sc_pools_and_sizes()
333 return -EINVAL; in init_sc_pools_and_sizes()
337 pool_blocks = total_blocks - fixed_blocks; in init_sc_pools_and_sizes()
343 return -EINVAL; in init_sc_pools_and_sizes()
346 pool_blocks -= ab_total; in init_sc_pools_and_sizes()
352 if (pi->centipercent >= 0) in init_sc_pools_and_sizes()
353 pi->blocks = (pool_blocks * pi->centipercent) / 10000; in init_sc_pools_and_sizes()
355 if (pi->blocks == 0 && pi->count != 0) { in init_sc_pools_and_sizes()
359 i, pi->count); in init_sc_pools_and_sizes()
360 return -EINVAL; in init_sc_pools_and_sizes()
362 if (pi->count == 0) { in init_sc_pools_and_sizes()
364 if (pi->blocks != 0) in init_sc_pools_and_sizes()
368 i, pi->blocks); in init_sc_pools_and_sizes()
369 pi->size = 0; in init_sc_pools_and_sizes()
371 pi->size = pi->blocks / pi->count; in init_sc_pools_and_sizes()
378 if (dd->sc_sizes[i].size < 0) { in init_sc_pools_and_sizes()
379 unsigned pool = wildcard_to_pool(dd->sc_sizes[i].size); in init_sc_pools_and_sizes()
382 dd->sc_sizes[i].size = mem_pool_info[pool].size; in init_sc_pools_and_sizes()
386 if (dd->sc_sizes[i].size > PIO_MAX_BLOCKS) in init_sc_pools_and_sizes()
387 dd->sc_sizes[i].size = PIO_MAX_BLOCKS; in init_sc_pools_and_sizes()
390 used_blocks += dd->sc_sizes[i].size * dd->sc_sizes[i].count; in init_sc_pools_and_sizes()
392 extra = total_blocks - used_blocks; in init_sc_pools_and_sizes()
408 dd->hw_to_sw = kmalloc_array(TXE_NUM_CONTEXTS, sizeof(u8), in init_send_contexts()
410 dd->send_contexts = kcalloc(dd->num_send_contexts, in init_send_contexts()
413 if (!dd->send_contexts || !dd->hw_to_sw) { in init_send_contexts()
414 kfree(dd->hw_to_sw); in init_send_contexts()
415 kfree(dd->send_contexts); in init_send_contexts()
417 return -ENOMEM; in init_send_contexts()
422 dd->hw_to_sw[i] = INVALID_SCI; in init_send_contexts()
431 struct sc_config_sizes *scs = &dd->sc_sizes[i]; in init_send_contexts()
433 for (j = 0; j < scs->count; j++) { in init_send_contexts()
435 &dd->send_contexts[context]; in init_send_contexts()
436 sci->type = i; in init_send_contexts()
437 sci->base = base; in init_send_contexts()
438 sci->credits = scs->size; in init_send_contexts()
441 base += scs->size; in init_send_contexts()
451 * Must be called with dd->sc_lock held.
460 for (index = 0, sci = &dd->send_contexts[0]; in sc_hw_alloc()
461 index < dd->num_send_contexts; index++, sci++) { in sc_hw_alloc()
462 if (sci->type == type && sci->allocated == 0) { in sc_hw_alloc()
463 sci->allocated = 1; in sc_hw_alloc()
464 /* use a 1:1 mapping, but make them non-equal */ in sc_hw_alloc()
465 context = chip_send_contexts(dd) - index - 1; in sc_hw_alloc()
466 dd->hw_to_sw[context] = index; in sc_hw_alloc()
473 return -ENOSPC; in sc_hw_alloc()
479 * Must be called with dd->sc_lock held.
485 sci = &dd->send_contexts[sw_index]; in sc_hw_free()
486 if (!sci->allocated) { in sc_hw_free()
490 sci->allocated = 0; in sc_hw_free()
491 dd->hw_to_sw[hw_context] = INVALID_SCI; in sc_hw_free()
521 u32 gc = group_context(sc->hw_context, sc->group); in cr_group_addresses()
522 u32 index = sc->hw_context & 0x7; in cr_group_addresses()
524 sc->hw_free = &sc->dd->cr_base[sc->node].va[gc].cr[index]; in cr_group_addresses()
526 &((struct credit_return *)sc->dd->cr_base[sc->node].dma)[gc]; in cr_group_addresses()
561 if (sc->credits <= release_credits) in sc_mtu_to_threshold()
564 threshold = sc->credits - release_credits; in sc_mtu_to_threshold()
578 return (sc->credits * percent) / 100; in sc_percent_to_threshold()
590 spin_lock_irqsave(&sc->credit_ctrl_lock, flags); in sc_set_cr_threshold()
592 old_threshold = (sc->credit_ctrl >> in sc_set_cr_threshold()
597 sc->credit_ctrl = in sc_set_cr_threshold()
598 (sc->credit_ctrl in sc_set_cr_threshold()
603 write_kctxt_csr(sc->dd, sc->hw_context, in sc_set_cr_threshold()
604 SC(CREDIT_CTRL), sc->credit_ctrl); in sc_set_cr_threshold()
610 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags); in sc_set_cr_threshold()
623 struct hfi1_devdata *dd = sc->dd; in set_pio_integrity()
624 u32 hw_context = sc->hw_context; in set_pio_integrity()
625 int type = sc->type; in set_pio_integrity()
638 ret += *per_cpu_ptr(sc->buffers_allocated, cpu); in get_buffers_allocated()
647 (*per_cpu_ptr(sc->buffers_allocated, cpu)) = 0; in reset_buffers_allocated()
669 if (dd->flags & HFI1_FROZEN) in sc_alloc()
676 sc->buffers_allocated = alloc_percpu(u32); in sc_alloc()
677 if (!sc->buffers_allocated) { in sc_alloc()
685 spin_lock_irqsave(&dd->sc_lock, flags); in sc_alloc()
688 spin_unlock_irqrestore(&dd->sc_lock, flags); in sc_alloc()
689 free_percpu(sc->buffers_allocated); in sc_alloc()
694 sci = &dd->send_contexts[sw_index]; in sc_alloc()
695 sci->sc = sc; in sc_alloc()
697 sc->dd = dd; in sc_alloc()
698 sc->node = numa; in sc_alloc()
699 sc->type = type; in sc_alloc()
700 spin_lock_init(&sc->alloc_lock); in sc_alloc()
701 spin_lock_init(&sc->release_lock); in sc_alloc()
702 spin_lock_init(&sc->credit_ctrl_lock); in sc_alloc()
703 seqlock_init(&sc->waitlock); in sc_alloc()
704 INIT_LIST_HEAD(&sc->piowait); in sc_alloc()
705 INIT_WORK(&sc->halt_work, sc_halted); in sc_alloc()
706 init_waitqueue_head(&sc->halt_wait); in sc_alloc()
709 sc->group = 0; in sc_alloc()
711 sc->sw_index = sw_index; in sc_alloc()
712 sc->hw_context = hw_context; in sc_alloc()
714 sc->credits = sci->credits; in sc_alloc()
715 sc->size = sc->credits * PIO_BLOCK_SIZE; in sc_alloc()
720 sc->base_addr = dd->piobase + ((hw_context & PIO_ADDR_CONTEXT_MASK) in sc_alloc()
724 reg = ((sci->credits & SC(CTRL_CTXT_DEPTH_MASK)) in sc_alloc()
726 | ((sci->base & SC(CTRL_CTXT_BASE_MASK)) in sc_alloc()
733 write_kctxt_csr(dd, hw_context, SC(ERR_MASK), (u64)-1); in sc_alloc()
764 * sanitized on driver start-up. in sc_alloc()
767 * work for both the 3-deep buffering allocation and the in sc_alloc()
787 /* set up write-through credit_ctrl */ in sc_alloc()
788 sc->credit_ctrl = reg; in sc_alloc()
797 spin_unlock_irqrestore(&dd->sc_lock, flags); in sc_alloc()
812 sc->sr_size = sci->credits + 1; in sc_alloc()
813 sc->sr = kcalloc_node(sc->sr_size, in sc_alloc()
816 if (!sc->sr) { in sc_alloc()
827 sc->group, in sc_alloc()
828 sc->credits, in sc_alloc()
829 sc->credit_ctrl, in sc_alloc()
835 /* free a per-NUMA send context structure */
846 sc->flags |= SCF_IN_FREE; /* ensure no restarts */ in sc_free()
847 dd = sc->dd; in sc_free()
848 if (!list_empty(&sc->piowait)) in sc_free()
850 sw_index = sc->sw_index; in sc_free()
851 hw_context = sc->hw_context; in sc_free()
853 flush_work(&sc->halt_work); in sc_free()
855 spin_lock_irqsave(&dd->sc_lock, flags); in sc_free()
856 dd->send_contexts[sw_index].sc = NULL; in sc_free()
867 /* release the index and context for re-use */ in sc_free()
869 spin_unlock_irqrestore(&dd->sc_lock, flags); in sc_free()
871 kfree(sc->sr); in sc_free()
872 free_percpu(sc->buffers_allocated); in sc_free()
887 spin_lock_irq(&sc->alloc_lock); in sc_disable()
888 reg = read_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL)); in sc_disable()
890 sc->flags &= ~SCF_ENABLED; in sc_disable()
892 write_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL), reg); in sc_disable()
897 * could be one in-process when the context is disabled). in sc_disable()
902 spin_lock(&sc->release_lock); in sc_disable()
903 if (sc->sr) { /* this context has a shadow ring */ in sc_disable()
904 while (sc->sr_tail != sc->sr_head) { in sc_disable()
905 pbuf = &sc->sr[sc->sr_tail].pbuf; in sc_disable()
906 if (pbuf->cb) in sc_disable()
907 (*pbuf->cb)(pbuf->arg, PRC_SC_DISABLE); in sc_disable()
908 sc->sr_tail++; in sc_disable()
909 if (sc->sr_tail >= sc->sr_size) in sc_disable()
910 sc->sr_tail = 0; in sc_disable()
913 spin_unlock(&sc->release_lock); in sc_disable()
915 write_seqlock(&sc->waitlock); in sc_disable()
916 list_splice_init(&sc->piowait, &wake_list); in sc_disable()
917 write_sequnlock(&sc->waitlock); in sc_disable()
925 priv = qp->priv; in sc_disable()
926 list_del_init(&priv->s_iowait.list); in sc_disable()
927 priv->s_iowait.lock = NULL; in sc_disable()
931 spin_unlock_irq(&sc->alloc_lock); in sc_disable()
956 * sc_wait_for_packet_egress - wait for packet
971 struct hfi1_devdata *dd = sc->dd; in sc_wait_for_packet_egress()
978 reg = read_csr(dd, sc->hw_context * 8 + in sc_wait_for_packet_egress()
981 if (sc->flags & SCF_HALTED || in sc_wait_for_packet_egress()
982 is_sc_halted(dd, sc->hw_context) || egress_halted(reg)) in sc_wait_for_packet_egress()
991 /* timed out - bounce the link */ in sc_wait_for_packet_egress()
993 … "%s: context %u(%u) timeout waiting for packets to egress, remaining count %u, bouncing link\n", in sc_wait_for_packet_egress()
994 __func__, sc->sw_index, in sc_wait_for_packet_egress()
995 sc->hw_context, (u32)reg); in sc_wait_for_packet_egress()
996 queue_work(dd->pport->link_wq, in sc_wait_for_packet_egress()
997 &dd->pport->link_bounce_work); in sc_wait_for_packet_egress()
1013 for (i = 0; i < dd->num_send_contexts; i++) { in sc_wait()
1014 struct send_context *sc = dd->send_contexts[i].sc; in sc_wait()
1025 * If the first step fails - wait for the halt to be asserted, return early.
1033 struct hfi1_devdata *dd = sc->dd; in sc_restart()
1039 if (!(sc->flags & SCF_HALTED) || (sc->flags & SCF_IN_FREE)) in sc_restart()
1040 return -EINVAL; in sc_restart()
1042 dd_dev_info(dd, "restarting send context %u(%u)\n", sc->sw_index, in sc_restart()
1043 sc->hw_context); in sc_restart()
1053 reg = read_kctxt_csr(dd, sc->hw_context, SC(STATUS)); in sc_restart()
1058 __func__, sc->sw_index, sc->hw_context); in sc_restart()
1059 return -ETIME; in sc_restart()
1075 if (sc->type != SC_USER) { in sc_restart()
1084 "%s: context %u(%u) timeout waiting for PIO buffers to zero, remaining %d\n", in sc_restart()
1085 __func__, sc->sw_index, in sc_restart()
1086 sc->hw_context, count); in sc_restart()
1107 * This enable will clear the halted flag and per-send context in sc_restart()
1123 for (i = 0; i < dd->num_send_contexts; i++) { in pio_freeze()
1124 sc = dd->send_contexts[i].sc; in pio_freeze()
1130 if (!sc || !(sc->flags & SCF_FROZEN) || sc->type == SC_USER) in pio_freeze()
1139 * Unfreeze PIO for kernel send contexts. The precondition for calling this
1141 * been cleared. Now perform the last step and re-enable each kernel context.
1150 for (i = 0; i < dd->num_send_contexts; i++) { in pio_kernel_unfreeze()
1151 sc = dd->send_contexts[i].sc; in pio_kernel_unfreeze()
1152 if (!sc || !(sc->flags & SCF_FROZEN) || sc->type == SC_USER) in pio_kernel_unfreeze()
1154 if (sc->flags & SCF_LINK_DOWN) in pio_kernel_unfreeze()
1162 * pio_kernel_linkup() - Re-enable send contexts after linkup event
1166 * event is different from a freeze because if the send context is re-enabled
1178 for (i = 0; i < dd->num_send_contexts; i++) { in pio_kernel_linkup()
1179 sc = dd->send_contexts[i].sc; in pio_kernel_linkup()
1180 if (!sc || !(sc->flags & SCF_LINK_DOWN) || sc->type == SC_USER) in pio_kernel_linkup()
1190 * -ETIMEDOUT - if we wait too long
1191 * -EIO - if there was an error
1199 max = (dd->icode == ICODE_FPGA_EMULATION) ? 120 : 5; in pio_init_wait_progress()
1205 return -ETIMEDOUT; in pio_init_wait_progress()
1210 return reg & SEND_PIO_INIT_CTXT_PIO_INIT_ERR_SMASK ? -EIO : 0; in pio_init_wait_progress()
1214 * Reset all of the send contexts to their power-on state. Used
1215 * only during manual init - no lock against sc_enable needed.
1223 /* ignore any timeout */ in pio_reset_all()
1224 if (ret == -EIO) { in pio_reset_all()
1238 ret == -ETIMEDOUT ? "is stuck" : "had an error"); in pio_reset_all()
1251 return -EINVAL; in sc_enable()
1252 dd = sc->dd; in sc_enable()
1261 spin_lock_irqsave(&sc->alloc_lock, flags); in sc_enable()
1262 sc_ctrl = read_kctxt_csr(dd, sc->hw_context, SC(CTRL)); in sc_enable()
1266 /* IMPORTANT: only clear free and fill if transitioning 0 -> 1 */ in sc_enable()
1268 *sc->hw_free = 0; in sc_enable()
1269 sc->free = 0; in sc_enable()
1270 sc->alloc_free = 0; in sc_enable()
1271 sc->fill = 0; in sc_enable()
1272 sc->fill_wrap = 0; in sc_enable()
1273 sc->sr_head = 0; in sc_enable()
1274 sc->sr_tail = 0; in sc_enable()
1275 sc->flags = 0; in sc_enable()
1280 * Clear all per-context errors. Some of these will be set when in sc_enable()
1281 * we are re-enabling after a context halt. Now that the context in sc_enable()
1285 reg = read_kctxt_csr(dd, sc->hw_context, SC(ERR_STATUS)); in sc_enable()
1287 write_kctxt_csr(dd, sc->hw_context, SC(ERR_CLEAR), reg); in sc_enable()
1293 spin_lock(&dd->sc_init_lock); in sc_enable()
1301 pio = ((sc->hw_context & SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_MASK) << in sc_enable()
1311 spin_unlock(&dd->sc_init_lock); in sc_enable()
1315 sc->sw_index, sc->hw_context, ret); in sc_enable()
1323 write_kctxt_csr(dd, sc->hw_context, SC(CTRL), sc_ctrl); in sc_enable()
1328 read_kctxt_csr(dd, sc->hw_context, SC(CTRL)); in sc_enable()
1329 sc->flags |= SCF_ENABLED; in sc_enable()
1332 spin_unlock_irqrestore(&sc->alloc_lock, flags); in sc_enable()
1343 /* a 0->1 transition schedules a credit return */ in sc_return_credits()
1344 write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE), in sc_return_credits()
1348 * scheduled. We care more about the 0 -> 1 transition. in sc_return_credits()
1350 read_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE)); in sc_return_credits()
1352 write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE), 0); in sc_return_credits()
1355 /* allow all in-flight packets to drain on the context */
1370 dd_dev_info(sc->dd, "%s: context %u(%u) - not implemented\n", in sc_drop()
1371 __func__, sc->sw_index, sc->hw_context); in sc_drop()
1376 * - mark the context as halted or frozen
1377 * - stop buffer allocations
1387 spin_lock_irqsave(&sc->alloc_lock, flags); in sc_stop()
1389 sc->flags |= flag; in sc_stop()
1390 sc->flags &= ~SCF_ENABLED; in sc_stop()
1391 spin_unlock_irqrestore(&sc->alloc_lock, flags); in sc_stop()
1392 wake_up(&sc->halt_wait); in sc_stop()
1402 * @len: length of whole packet - including PBC - in dwords
1406 * Return a pointer to a PIO buffer, NULL if not enough room, -ECOMM
1420 spin_lock_irqsave(&sc->alloc_lock, flags); in sc_buffer_alloc()
1421 if (!(sc->flags & SCF_ENABLED)) { in sc_buffer_alloc()
1422 spin_unlock_irqrestore(&sc->alloc_lock, flags); in sc_buffer_alloc()
1423 return ERR_PTR(-ECOMM); in sc_buffer_alloc()
1427 avail = (unsigned long)sc->credits - (sc->fill - sc->alloc_free); in sc_buffer_alloc()
1431 spin_unlock_irqrestore(&sc->alloc_lock, flags); in sc_buffer_alloc()
1435 sc->alloc_free = READ_ONCE(sc->free); in sc_buffer_alloc()
1437 (unsigned long)sc->credits - in sc_buffer_alloc()
1438 (sc->fill - sc->alloc_free); in sc_buffer_alloc()
1442 sc->alloc_free = READ_ONCE(sc->free); in sc_buffer_alloc()
1451 this_cpu_inc(*sc->buffers_allocated); in sc_buffer_alloc()
1454 head = sc->sr_head; in sc_buffer_alloc()
1457 sc->fill += blocks; in sc_buffer_alloc()
1458 fill_wrap = sc->fill_wrap; in sc_buffer_alloc()
1459 sc->fill_wrap += blocks; in sc_buffer_alloc()
1460 if (sc->fill_wrap >= sc->credits) in sc_buffer_alloc()
1461 sc->fill_wrap = sc->fill_wrap - sc->credits; in sc_buffer_alloc()
1470 pbuf = &sc->sr[head].pbuf; in sc_buffer_alloc()
1471 pbuf->sent_at = sc->fill; in sc_buffer_alloc()
1472 pbuf->cb = cb; in sc_buffer_alloc()
1473 pbuf->arg = arg; in sc_buffer_alloc()
1474 pbuf->sc = sc; /* could be filled in at sc->sr init time */ in sc_buffer_alloc()
1479 if (next >= sc->sr_size) in sc_buffer_alloc()
1482 * update the head - must be last! - the releaser can look at fields in sc_buffer_alloc()
1486 sc->sr_head = next; in sc_buffer_alloc()
1487 spin_unlock_irqrestore(&sc->alloc_lock, flags); in sc_buffer_alloc()
1490 pbuf->start = sc->base_addr + fill_wrap * PIO_BLOCK_SIZE; in sc_buffer_alloc()
1491 pbuf->end = sc->base_addr + sc->size; in sc_buffer_alloc()
1492 pbuf->qw_written = 0; in sc_buffer_alloc()
1493 pbuf->carry_bytes = 0; in sc_buffer_alloc()
1494 pbuf->carry.val64 = 0; in sc_buffer_alloc()
1515 spin_lock_irqsave(&sc->credit_ctrl_lock, flags); in sc_add_credit_return_intr()
1516 if (sc->credit_intr_count == 0) { in sc_add_credit_return_intr()
1517 sc->credit_ctrl |= SC(CREDIT_CTRL_CREDIT_INTR_SMASK); in sc_add_credit_return_intr()
1518 write_kctxt_csr(sc->dd, sc->hw_context, in sc_add_credit_return_intr()
1519 SC(CREDIT_CTRL), sc->credit_ctrl); in sc_add_credit_return_intr()
1521 sc->credit_intr_count++; in sc_add_credit_return_intr()
1522 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags); in sc_add_credit_return_intr()
1533 WARN_ON(sc->credit_intr_count == 0); in sc_del_credit_return_intr()
1536 spin_lock_irqsave(&sc->credit_ctrl_lock, flags); in sc_del_credit_return_intr()
1537 sc->credit_intr_count--; in sc_del_credit_return_intr()
1538 if (sc->credit_intr_count == 0) { in sc_del_credit_return_intr()
1539 sc->credit_ctrl &= ~SC(CREDIT_CTRL_CREDIT_INTR_SMASK); in sc_del_credit_return_intr()
1540 write_kctxt_csr(sc->dd, sc->hw_context, in sc_del_credit_return_intr()
1541 SC(CREDIT_CTRL), sc->credit_ctrl); in sc_del_credit_return_intr()
1543 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags); in sc_del_credit_return_intr()
1556 trace_hfi1_wantpiointr(sc, needint, sc->credit_ctrl); in hfi1_sc_wantpiobuf_intr()
1562 * sc_piobufavail - callback when a PIO buffer is available
1571 struct hfi1_devdata *dd = sc->dd; in sc_piobufavail()
1579 if (dd->send_contexts[sc->sw_index].type != SC_KERNEL && in sc_piobufavail()
1580 dd->send_contexts[sc->sw_index].type != SC_VL15) in sc_piobufavail()
1582 list = &sc->piowait; in sc_piobufavail()
1589 write_seqlock_irqsave(&sc->waitlock, flags); in sc_piobufavail()
1598 priv = qp->priv; in sc_piobufavail()
1599 list_del_init(&priv->s_iowait.list); in sc_piobufavail()
1600 priv->s_iowait.lock = NULL; in sc_piobufavail()
1602 priv = qps[top_idx]->priv; in sc_piobufavail()
1604 &priv->s_iowait, in sc_piobufavail()
1620 write_sequnlock_irqrestore(&sc->waitlock, flags); in sc_piobufavail()
1622 /* Wake up the top-priority one first */ in sc_piobufavail()
1670 spin_lock_irqsave(&sc->release_lock, flags); in sc_release_update()
1672 hw_free = le64_to_cpu(*sc->hw_free); /* volatile read */ in sc_release_update()
1673 old_free = sc->free; in sc_release_update()
1675 - (old_free & CR_COUNTER_MASK)) in sc_release_update()
1681 code = -1; /* code not yet set */ in sc_release_update()
1682 head = READ_ONCE(sc->sr_head); /* snapshot the head */ in sc_release_update()
1683 tail = sc->sr_tail; in sc_release_update()
1685 pbuf = &sc->sr[tail].pbuf; in sc_release_update()
1687 if (sent_before(free, pbuf->sent_at)) { in sc_release_update()
1691 if (pbuf->cb) { in sc_release_update()
1694 (*pbuf->cb)(pbuf->arg, code); in sc_release_update()
1698 if (tail >= sc->sr_size) in sc_release_update()
1701 sc->sr_tail = tail; in sc_release_update()
1704 sc->free = free; in sc_release_update()
1705 spin_unlock_irqrestore(&sc->release_lock, flags); in sc_release_update()
1724 spin_lock(&dd->sc_lock); in sc_group_release_update()
1725 sw_index = dd->hw_to_sw[hw_context]; in sc_group_release_update()
1726 if (unlikely(sw_index >= dd->num_send_contexts)) { in sc_group_release_update()
1731 sc = dd->send_contexts[sw_index].sc; in sc_group_release_update()
1735 gc = group_context(hw_context, sc->group); in sc_group_release_update()
1736 gc_end = gc + group_size(sc->group); in sc_group_release_update()
1738 sw_index = dd->hw_to_sw[gc]; in sc_group_release_update()
1739 if (unlikely(sw_index >= dd->num_send_contexts)) { in sc_group_release_update()
1745 sc_release_update(dd->send_contexts[sw_index].sc); in sc_group_release_update()
1748 spin_unlock(&dd->sc_lock); in sc_group_release_update()
1752 * pio_select_send_context_vl() - select send context
1768 * NOTE This should only happen if SC->VL changed after the initial in pio_select_send_context_vl()
1778 m = rcu_dereference(dd->pio_map); in pio_select_send_context_vl()
1781 return dd->vld[0].sc; in pio_select_send_context_vl()
1783 e = m->map[vl & m->mask]; in pio_select_send_context_vl()
1784 rval = e->ksc[selector & e->mask]; in pio_select_send_context_vl()
1788 rval = !rval ? dd->vld[0].sc : rval; in pio_select_send_context_vl()
1793 * pio_select_send_context_sc() - select send context
1815 for (i = 0; m && i < m->actual_vls; i++) in pio_map_free()
1816 kfree(m->map[i]); in pio_map_free()
1837 thres = min(sc_percent_to_threshold(dd->kernel_send_context[scontext], in set_threshold()
1839 sc_mtu_to_threshold(dd->kernel_send_context[scontext], in set_threshold()
1840 dd->vld[i].mtu, in set_threshold()
1841 dd->rcd[0]->rcvhdrqentsize)); in set_threshold()
1842 sc_set_cr_threshold(dd->kernel_send_context[scontext], thres); in set_threshold()
1846 * pio_map_init - called when #vls change
1854 * vl_scontexts is used to specify a non-uniform vl/send context
1864 * If either the num_vls or num_send_contexts are non-power of 2, the
1883 for (i = 0; i < dd->num_send_contexts; i++) in pio_map_init()
1884 if (dd->send_contexts[i].type == SC_KERNEL) in pio_map_init()
1892 for (i = num_vls - 1; i >= 0; i--, extra--) in pio_map_init()
1900 newmap->actual_vls = num_vls; in pio_map_init()
1901 newmap->vls = roundup_pow_of_two(num_vls); in pio_map_init()
1902 newmap->mask = (1 << ilog2(newmap->vls)) - 1; in pio_map_init()
1903 for (i = 0; i < newmap->vls; i++) { in pio_map_init()
1907 if (i < newmap->actual_vls) { in pio_map_init()
1911 newmap->map[i] = kzalloc(struct_size(newmap->map[i], in pio_map_init()
1914 if (!newmap->map[i]) in pio_map_init()
1916 newmap->map[i]->mask = (1 << ilog2(sz)) - 1; in pio_map_init()
1922 if (dd->kernel_send_context[scontext]) { in pio_map_init()
1923 newmap->map[i]->ksc[j] = in pio_map_init()
1924 dd->kernel_send_context[scontext]; in pio_map_init()
1933 /* just re-use entry without allocating */ in pio_map_init()
1934 newmap->map[i] = newmap->map[i % num_vls]; in pio_map_init()
1939 spin_lock_irq(&dd->pio_map_lock); in pio_map_init()
1940 oldmap = rcu_dereference_protected(dd->pio_map, in pio_map_init()
1941 lockdep_is_held(&dd->pio_map_lock)); in pio_map_init()
1944 rcu_assign_pointer(dd->pio_map, newmap); in pio_map_init()
1946 spin_unlock_irq(&dd->pio_map_lock); in pio_map_init()
1949 call_rcu(&oldmap->list, pio_map_rcu_callback); in pio_map_init()
1954 return -ENOMEM; in pio_map_init()
1960 if (rcu_access_pointer(dd->pio_map)) { in free_pio_map()
1961 spin_lock_irq(&dd->pio_map_lock); in free_pio_map()
1962 pio_map_free(rcu_access_pointer(dd->pio_map)); in free_pio_map()
1963 RCU_INIT_POINTER(dd->pio_map, NULL); in free_pio_map()
1964 spin_unlock_irq(&dd->pio_map_lock); in free_pio_map()
1967 kfree(dd->kernel_send_context); in free_pio_map()
1968 dd->kernel_send_context = NULL; in free_pio_map()
1974 u64 mask, all_vl_mask = (u64)0x80ff; /* VLs 0-7, 15 */ in init_pervl_scs()
1975 u64 data_vls_mask = (u64)0x00ff; /* VLs 0-7 */ in init_pervl_scs()
1977 struct hfi1_pportdata *ppd = dd->pport; in init_pervl_scs()
1979 dd->vld[15].sc = sc_alloc(dd, SC_VL15, in init_pervl_scs()
1980 dd->rcd[0]->rcvhdrqentsize, dd->node); in init_pervl_scs()
1981 if (!dd->vld[15].sc) in init_pervl_scs()
1982 return -ENOMEM; in init_pervl_scs()
1984 hfi1_init_ctxt(dd->vld[15].sc); in init_pervl_scs()
1985 dd->vld[15].mtu = enum_to_mtu(OPA_MTU_2048); in init_pervl_scs()
1987 dd->kernel_send_context = kcalloc_node(dd->num_send_contexts, in init_pervl_scs()
1989 GFP_KERNEL, dd->node); in init_pervl_scs()
1990 if (!dd->kernel_send_context) in init_pervl_scs()
1993 dd->kernel_send_context[0] = dd->vld[15].sc; in init_pervl_scs()
2003 dd->vld[i].sc = sc_alloc(dd, SC_KERNEL, in init_pervl_scs()
2004 dd->rcd[0]->rcvhdrqentsize, dd->node); in init_pervl_scs()
2005 if (!dd->vld[i].sc) in init_pervl_scs()
2007 dd->kernel_send_context[i + 1] = dd->vld[i].sc; in init_pervl_scs()
2008 hfi1_init_ctxt(dd->vld[i].sc); in init_pervl_scs()
2010 dd->vld[i].mtu = hfi1_max_mtu; in init_pervl_scs()
2013 dd->kernel_send_context[i + 1] = in init_pervl_scs()
2014 sc_alloc(dd, SC_KERNEL, dd->rcd[0]->rcvhdrqentsize, dd->node); in init_pervl_scs()
2015 if (!dd->kernel_send_context[i + 1]) in init_pervl_scs()
2017 hfi1_init_ctxt(dd->kernel_send_context[i + 1]); in init_pervl_scs()
2020 sc_enable(dd->vld[15].sc); in init_pervl_scs()
2021 ctxt = dd->vld[15].sc->hw_context; in init_pervl_scs()
2026 dd->vld[15].sc->sw_index, ctxt); in init_pervl_scs()
2029 sc_enable(dd->vld[i].sc); in init_pervl_scs()
2030 ctxt = dd->vld[i].sc->hw_context; in init_pervl_scs()
2035 sc_enable(dd->kernel_send_context[i + 1]); in init_pervl_scs()
2036 ctxt = dd->kernel_send_context[i + 1]->hw_context; in init_pervl_scs()
2041 if (pio_map_init(dd, ppd->port - 1, num_vls, NULL)) in init_pervl_scs()
2047 sc_free(dd->vld[i].sc); in init_pervl_scs()
2048 dd->vld[i].sc = NULL; in init_pervl_scs()
2052 sc_free(dd->kernel_send_context[i + 1]); in init_pervl_scs()
2054 kfree(dd->kernel_send_context); in init_pervl_scs()
2055 dd->kernel_send_context = NULL; in init_pervl_scs()
2058 sc_free(dd->vld[15].sc); in init_pervl_scs()
2059 return -ENOMEM; in init_pervl_scs()
2067 dd->cr_base = kcalloc( in init_credit_return()
2071 if (!dd->cr_base) { in init_credit_return()
2072 ret = -ENOMEM; in init_credit_return()
2078 set_dev_node(&dd->pcidev->dev, i); in init_credit_return()
2079 dd->cr_base[i].va = dma_alloc_coherent(&dd->pcidev->dev, in init_credit_return()
2081 &dd->cr_base[i].dma, in init_credit_return()
2083 if (!dd->cr_base[i].va) { in init_credit_return()
2084 set_dev_node(&dd->pcidev->dev, dd->node); in init_credit_return()
2088 ret = -ENOMEM; in init_credit_return()
2092 set_dev_node(&dd->pcidev->dev, dd->node); in init_credit_return()
2107 if (!dd->cr_base) in free_credit_return()
2110 if (dd->cr_base[i].va) { in free_credit_return()
2111 dma_free_coherent(&dd->pcidev->dev, in free_credit_return()
2114 dd->cr_base[i].va, in free_credit_return()
2115 dd->cr_base[i].dma); in free_credit_return()
2118 kfree(dd->cr_base); in free_credit_return()
2119 dd->cr_base = NULL; in free_credit_return()
2125 struct send_context *sc = sci->sc; in seqfile_dump_sci()
2129 i, sci->type, sci->base, sci->credits); in seqfile_dump_sci()
2131 sc->flags, sc->sw_index, sc->hw_context, sc->group); in seqfile_dump_sci()
2133 sc->sr_size, sc->credits, sc->sr_head, sc->sr_tail); in seqfile_dump_sci()
2135 sc->fill, sc->free, sc->fill_wrap, sc->alloc_free); in seqfile_dump_sci()
2137 sc->credit_intr_count, sc->credit_ctrl); in seqfile_dump_sci()
2138 reg = read_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_STATUS)); in seqfile_dump_sci()
2140 (le64_to_cpu(*sc->hw_free) & CR_COUNTER_SMASK) >> in seqfile_dump_sci()