Lines Matching refs:write_csr
1321 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value) in write_csr() function
1358 write_csr(dd, csr, value); in read_write_csr()
5684 write_csr(dd, SEND_EGRESS_ERR_INFO, info); in handle_send_egress_err_info()
6100 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : in handle_qsfp_int()
6136 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : in handle_qsfp_int()
6191 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, in set_host_lcb_access()
6202 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, in set_8051_lcb_access()
6326 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, in hreq_response()
6348 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0); in handle_8051_request()
6369 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET); in handle_8051_request()
6375 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); in handle_8051_request()
6403 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); in set_up_vau()
6424 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); in set_up_vl15()
6426 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf in set_up_vl15()
6440 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); in reset_link_credits()
6441 write_csr(dd, SEND_CM_CREDIT_VL15, 0); in reset_link_credits()
6442 write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0); in reset_link_credits()
6481 write_csr(dd, DC_LCB_CFG_RUN, 0); in lcb_shutdown()
6483 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, in lcb_shutdown()
6488 write_csr(dd, DCC_CFG_RESET, reg | in lcb_shutdown()
6493 write_csr(dd, DCC_CFG_RESET, reg); in lcb_shutdown()
6494 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); in lcb_shutdown()
6523 write_csr(dd, DC_DC8051_CFG_RST, 0x1); in _dc_shutdown()
6547 write_csr(dd, DC_DC8051_CFG_RST, 0ull); in _dc_start()
6554 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); in _dc_start()
6556 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); in _dc_start()
6634 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull); in adjust_lcb_for_fpga_serdes()
6645 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr); in adjust_lcb_for_fpga_serdes()
6647 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, in adjust_lcb_for_fpga_serdes()
6649 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr); in adjust_lcb_for_fpga_serdes()
6722 write_csr(dd, RCV_CTRL, rcvctrl); in adjust_rcvctrl()
6747 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); in start_freeze_handling()
6896 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); in handle_freeze()
6900 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); in handle_freeze()
6902 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); in handle_freeze()
7500 write_csr(dd, DC_LCB_CFG_CRC_MODE, in handle_verify_cap()
7506 write_csr(dd, SEND_CM_CTRL, in handle_verify_cap()
7509 write_csr(dd, SEND_CM_CTRL, in handle_verify_cap()
7570 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg); in handle_verify_cap()
7574 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); in handle_verify_cap()
7577 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ in handle_verify_cap()
7845 write_csr(dd, DC_DC8051_ERR_EN, in handle_8051_interrupt()
8308 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]); in general_interrupt()
8341 write_csr(dd, in sdma_interrupt()
8364 write_csr(dd, addr, rcd->imask); in clear_recv_intr()
8372 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask); in force_recv_intr()
8565 write_csr(dd, DCC_CFG_PORT_CONFIG, reg); in set_logical_state()
8673 write_csr(dd, addr, data); in write_lcb_via_8051()
8703 write_csr(dd, addr, data); in write_lcb_csr()
8776 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg); in do_8051_command()
8787 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); in do_8051_command()
8789 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); in do_8051_command()
8826 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0); in do_8051_command()
9200 write_csr(dd, DC_LCB_CFG_LOOPBACK, in do_quick_linkup()
9202 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); in do_quick_linkup()
9207 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); in do_quick_linkup()
9212 write_csr(dd, DC_LCB_CFG_RUN, in do_quick_linkup()
9219 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, in do_quick_linkup()
9237 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ in do_quick_linkup()
9252 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ in do_quick_linkup()
9270 write_csr(dd, DC_DC8051_CFG_MODE, in init_loopback()
9512 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, in set_qsfp_int_n()
9518 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask); in set_qsfp_int_n()
9535 write_csr(dd, in reset_qsfp()
9541 write_csr(dd, in reset_qsfp()
9729 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, in init_qsfp_int()
9731 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, in init_qsfp_int()
9739 write_csr(dd, in init_qsfp_int()
9762 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01); in init_lcb()
9763 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00); in init_lcb()
9764 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00); in init_lcb()
9765 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); in init_lcb()
9766 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08); in init_lcb()
9767 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02); in init_lcb()
9768 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00); in init_lcb()
10140 write_csr(dd, SEND_LEN_CHECK0, len1); in set_send_length()
10141 write_csr(dd, SEND_LEN_CHECK1, len2); in set_send_length()
10167 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1); in set_send_length()
10190 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1); in set_lidlmc()
10369 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); in force_logical_link_state_down()
10370 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, in force_logical_link_state_down()
10373 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); in force_logical_link_state_down()
10374 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0); in force_logical_link_state_down()
10375 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); in force_logical_link_state_down()
10376 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2); in force_logical_link_state_down()
10378 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); in force_logical_link_state_down()
10381 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1); in force_logical_link_state_down()
10382 write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT); in force_logical_link_state_down()
10389 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); in force_logical_link_state_down()
10390 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0); in force_logical_link_state_down()
10391 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0); in force_logical_link_state_down()
10466 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ in goto_offline()
10822 write_csr(dd, DCC_CFG_LED_CNTRL, 0); in set_link_state()
10986 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg); in hfi1_set_ib_cfg()
11158 write_csr(dd, target + (i * 8), reg); in set_vl_weights()
11254 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, in set_sc2vlnt()
11272 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, in set_sc2vlnt()
11308 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); in set_global_shared()
11319 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); in set_global_limit()
11336 write_csr(dd, addr, reg); in set_vl_shared()
11353 write_csr(dd, addr, reg); in set_vl_dedicated()
12076 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT); in hfi1_rcvctrl()
12079 write_csr(dd, RCV_VL15, 0); in hfi1_rcvctrl()
13196 write_csr(dd, CCE_INT_MASK + (8 * idx), reg); in read_mod_write()
13243 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0); in clear_all_interrupts()
13245 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13246 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13247 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13248 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13249 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13250 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13251 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13257 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0); in clear_all_interrupts()
13258 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0); in clear_all_interrupts()
13259 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0); in clear_all_interrupts()
13287 write_csr(dd, CCE_INT_MAP + (8 * m), reg); in remap_intr()
13318 write_csr(dd, CCE_INT_MAP + (8 * i), 0); in reset_interrupts()
13541 write_csr(dd, RCV_PARTITION_KEY + in set_partition_keys()
13565 write_csr(dd, CCE_INT_MAP + (8 * i), 0); in write_uninitialized_csrs_and_memories()
13594 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); in write_uninitialized_csrs_and_memories()
13612 write_csr(dd, CCE_CTRL, ctrl_bits); in clear_cce_status()
13643 write_csr(dd, CCE_SCRATCH + (8 * i), 0); in reset_cce_csrs()
13645 write_csr(dd, CCE_ERR_MASK, 0); in reset_cce_csrs()
13646 write_csr(dd, CCE_ERR_CLEAR, ~0ull); in reset_cce_csrs()
13649 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0); in reset_cce_csrs()
13650 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR); in reset_cce_csrs()
13653 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0); in reset_cce_csrs()
13654 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i), in reset_cce_csrs()
13659 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull); in reset_cce_csrs()
13660 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull); in reset_cce_csrs()
13663 write_csr(dd, CCE_INT_MAP, 0); in reset_cce_csrs()
13666 write_csr(dd, CCE_INT_MASK + (8 * i), 0); in reset_cce_csrs()
13667 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull); in reset_cce_csrs()
13672 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0); in reset_cce_csrs()
13681 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0); in reset_misc_csrs()
13682 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0); in reset_misc_csrs()
13683 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0); in reset_misc_csrs()
13690 write_csr(dd, MISC_CFG_RSA_CMD, 1); in reset_misc_csrs()
13691 write_csr(dd, MISC_CFG_RSA_MU, 0); in reset_misc_csrs()
13692 write_csr(dd, MISC_CFG_FW_CTRL, 0); in reset_misc_csrs()
13698 write_csr(dd, MISC_ERR_MASK, 0); in reset_misc_csrs()
13699 write_csr(dd, MISC_ERR_CLEAR, ~0ull); in reset_misc_csrs()
13711 write_csr(dd, SEND_CTRL, 0); in reset_txe_csrs()
13717 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0); in reset_txe_csrs()
13720 write_csr(dd, SEND_PIO_ERR_MASK, 0); in reset_txe_csrs()
13721 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull); in reset_txe_csrs()
13724 write_csr(dd, SEND_DMA_ERR_MASK, 0); in reset_txe_csrs()
13725 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull); in reset_txe_csrs()
13728 write_csr(dd, SEND_EGRESS_ERR_MASK, 0); in reset_txe_csrs()
13729 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull); in reset_txe_csrs()
13731 write_csr(dd, SEND_BTH_QP, 0); in reset_txe_csrs()
13732 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0); in reset_txe_csrs()
13733 write_csr(dd, SEND_SC2VLT0, 0); in reset_txe_csrs()
13734 write_csr(dd, SEND_SC2VLT1, 0); in reset_txe_csrs()
13735 write_csr(dd, SEND_SC2VLT2, 0); in reset_txe_csrs()
13736 write_csr(dd, SEND_SC2VLT3, 0); in reset_txe_csrs()
13737 write_csr(dd, SEND_LEN_CHECK0, 0); in reset_txe_csrs()
13738 write_csr(dd, SEND_LEN_CHECK1, 0); in reset_txe_csrs()
13740 write_csr(dd, SEND_ERR_MASK, 0); in reset_txe_csrs()
13741 write_csr(dd, SEND_ERR_CLEAR, ~0ull); in reset_txe_csrs()
13744 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0); in reset_txe_csrs()
13746 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0); in reset_txe_csrs()
13748 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0); in reset_txe_csrs()
13750 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0); in reset_txe_csrs()
13752 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0); in reset_txe_csrs()
13753 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR); in reset_txe_csrs()
13754 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR); in reset_txe_csrs()
13756 write_csr(dd, SEND_CM_TIMER_CTRL, 0); in reset_txe_csrs()
13757 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0); in reset_txe_csrs()
13758 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0); in reset_txe_csrs()
13759 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0); in reset_txe_csrs()
13760 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0); in reset_txe_csrs()
13762 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); in reset_txe_csrs()
13763 write_csr(dd, SEND_CM_CREDIT_VL15, 0); in reset_txe_csrs()
13768 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull); in reset_txe_csrs()
13856 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK); in init_rbufs()
13893 write_csr(dd, RCV_CTRL, 0); in reset_rxe_csrs()
13899 write_csr(dd, RCV_BTH_QP, 0); in reset_rxe_csrs()
13900 write_csr(dd, RCV_MULTICAST, 0); in reset_rxe_csrs()
13901 write_csr(dd, RCV_BYPASS, 0); in reset_rxe_csrs()
13902 write_csr(dd, RCV_VL15, 0); in reset_rxe_csrs()
13904 write_csr(dd, RCV_ERR_INFO, in reset_rxe_csrs()
13907 write_csr(dd, RCV_ERR_MASK, 0); in reset_rxe_csrs()
13908 write_csr(dd, RCV_ERR_CLEAR, ~0ull); in reset_rxe_csrs()
13911 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); in reset_rxe_csrs()
13913 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0); in reset_rxe_csrs()
13915 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0); in reset_rxe_csrs()
13917 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0); in reset_rxe_csrs()
13921 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0); in reset_rxe_csrs()
13971 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL( in init_sc2vl_tables()
13977 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL( in init_sc2vl_tables()
13983 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL( in init_sc2vl_tables()
13989 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL( in init_sc2vl_tables()
13997 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL( in init_sc2vl_tables()
14001 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL( in init_sc2vl_tables()
14041 write_csr(dd, SEND_CTRL, 0); in init_chip()
14047 write_csr(dd, RCV_CTRL, 0); in init_chip()
14049 write_csr(dd, RCV_CTXT_CTRL, 0); in init_chip()
14052 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull); in init_chip()
14060 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); in init_chip()
14100 write_csr(dd, CCE_DC_CTRL, 0); in init_chip()
14115 write_csr(dd, ASIC_QSFP1_OUT, 0x1f); in init_chip()
14116 write_csr(dd, ASIC_QSFP2_OUT, 0x1f); in init_chip()
14149 write_csr(dd, SEND_BTH_QP, in init_kdeth_qp()
14153 write_csr(dd, RCV_BTH_QP, in init_kdeth_qp()
14203 write_csr(dd, regno, reg); in init_qpmap_table()
14263 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]); in complete_rsm_map_table()
14282 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), in add_rsm_rule()
14286 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), in add_rsm_rule()
14293 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), in add_rsm_rule()
14305 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0); in clear_rsm_rule()
14306 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0); in clear_rsm_rule()
14307 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0); in clear_rsm_rule()
14558 write_csr(dd, regoff, reg); in hfi1_netdev_update_rmt()
14652 write_csr(dd, RCV_ERR_MASK, ~0ull); in init_rxe()
14683 write_csr(dd, RCV_BYPASS, val); in init_rxe()
14690 write_csr(dd, CCE_ERR_MASK, ~0ull); in init_other()
14692 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK); in init_other()
14694 write_csr(dd, DCC_ERR_FLG_EN, ~0ull); in init_other()
14695 write_csr(dd, DC_DC8051_ERR_EN, ~0ull); in init_other()
14709 write_csr(dd, csr0to3, in assign_cm_au_table()
14716 write_csr(dd, csr4to7, in assign_cm_au_table()
14744 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull); in init_txe()
14745 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull); in init_txe()
14746 write_csr(dd, SEND_ERR_MASK, ~0ull); in init_txe()
14747 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull); in init_txe()
14763 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE); in init_txe()
14965 write_csr(dd, CCE_INT_MASK, 0ull); in check_int_registers()
14971 write_csr(dd, CCE_INT_CLEAR, all_bits); in check_int_registers()
14977 write_csr(dd, CCE_INT_FORCE, all_bits); in check_int_registers()
14983 write_csr(dd, CCE_INT_CLEAR, all_bits); in check_int_registers()
14984 write_csr(dd, CCE_INT_MASK, mask); in check_int_registers()
14988 write_csr(dd, CCE_INT_MASK, mask); in check_int_registers()
15415 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); in thermal_init()
15458 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); in thermal_init()