Lines Matching +full:vco +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0
63 #define ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */
64 #define ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */
65 #define ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */
66 #define ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */
67 #define ADF4371_MAX_OUT_RF32_FREQ (ADF4371_MAX_VCO_FREQ * 4) /* Hz */
68 #define ADF4371_MIN_OUT_RF32_FREQ (ADF4371_MIN_VCO_FREQ * 4) /* Hz */
70 #define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */
71 #define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */
73 /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
75 /* MOD2 is the programmable, 14-bit auxiliary fractional modulus */
187 val = (((u64)st->integer * ADF4371_MODULUS1) + st->fract1) * st->fpfd; in adf4371_pll_fract_n_get_rate()
188 tmp = (u64)st->fract2 * st->fpfd; in adf4371_pll_fract_n_get_rate()
189 do_div(tmp, st->mod2); in adf4371_pll_fract_n_get_rate()
193 ref_div_sel = st->rf_div_sel; in adf4371_pll_fract_n_get_rate()
207 static void adf4371_pll_fract_n_compute(unsigned long long vco, in adf4371_pll_fract_n_compute() argument
217 tmp = do_div(vco, pfd); in adf4371_pll_fract_n_compute()
221 *integer = vco; in adf4371_pll_fract_n_compute()
247 return -EINVAL; in adf4371_set_freq()
249 st->rf_div_sel = 0; in adf4371_set_freq()
253 st->rf_div_sel++; in adf4371_set_freq()
259 return -EINVAL; in adf4371_set_freq()
266 return -EINVAL; in adf4371_set_freq()
271 return -EINVAL; in adf4371_set_freq()
274 adf4371_pll_fract_n_compute(freq, st->fpfd, &st->integer, &st->fract1, in adf4371_set_freq()
275 &st->fract2, &st->mod2); in adf4371_set_freq()
276 st->buf[0] = st->integer >> 8; in adf4371_set_freq()
277 st->buf[1] = 0x40; /* REG12 default */ in adf4371_set_freq()
278 st->buf[2] = 0x00; in adf4371_set_freq()
279 st->buf[3] = st->fract1 & 0xFF; in adf4371_set_freq()
280 st->buf[4] = st->fract1 >> 8; in adf4371_set_freq()
281 st->buf[5] = st->fract1 >> 16; in adf4371_set_freq()
282 st->buf[6] = ADF4371_FRAC2WORD_L(st->fract2 & 0x7F) | in adf4371_set_freq()
283 ADF4371_FRAC1WORD(st->fract1 >> 24); in adf4371_set_freq()
284 st->buf[7] = ADF4371_FRAC2WORD_H(st->fract2 >> 7); in adf4371_set_freq()
285 st->buf[8] = st->mod2 & 0xFF; in adf4371_set_freq()
286 st->buf[9] = ADF4371_MOD2WORD(st->mod2 >> 8); in adf4371_set_freq()
288 ret = regmap_bulk_write(st->regmap, ADF4371_REG(0x11), st->buf, 10); in adf4371_set_freq()
295 ret = regmap_write(st->regmap, ADF4371_REG(0x1F), st->ref_div_factor); in adf4371_set_freq()
299 ret = regmap_update_bits(st->regmap, ADF4371_REG(0x24), in adf4371_set_freq()
301 ADF4371_RF_DIV_SEL(st->rf_div_sel)); in adf4371_set_freq()
305 cp_bleed = DIV_ROUND_UP(400 * 1750, st->integer * 375); in adf4371_set_freq()
307 ret = regmap_write(st->regmap, ADF4371_REG(0x26), cp_bleed); in adf4371_set_freq()
314 if (st->fract1 == 0 && st->fract2 == 0) in adf4371_set_freq()
317 ret = regmap_write(st->regmap, ADF4371_REG(0x2B), int_mode); in adf4371_set_freq()
321 return regmap_write(st->regmap, ADF4371_REG(0x10), st->integer & 0xFF); in adf4371_set_freq()
336 val = adf4371_pll_fract_n_get_rate(st, chan->channel); in adf4371_read()
337 ret = regmap_read(st->regmap, ADF4371_REG(0x7C), &readval); in adf4371_read()
342 dev_dbg(&st->spi->dev, "PLL un-locked\n"); in adf4371_read()
343 ret = -EBUSY; in adf4371_read()
347 reg = adf4371_pwrdown_ch[chan->channel].reg; in adf4371_read()
348 bit = adf4371_pwrdown_ch[chan->channel].bit; in adf4371_read()
350 ret = regmap_read(st->regmap, reg, &readval); in adf4371_read()
357 return sprintf(buf, "%s\n", adf4371_ch_names[chan->channel]); in adf4371_read()
359 ret = -EINVAL; in adf4371_read()
378 mutex_lock(&st->lock); in adf4371_write()
385 ret = adf4371_set_freq(st, freq, chan->channel); in adf4371_write()
392 reg = adf4371_pwrdown_ch[chan->channel].reg; in adf4371_write()
393 bit = adf4371_pwrdown_ch[chan->channel].bit; in adf4371_write()
394 ret = regmap_read(st->regmap, reg, &readval); in adf4371_write()
401 ret = regmap_write(st->regmap, reg, readval); in adf4371_write()
404 ret = -EINVAL; in adf4371_write()
407 mutex_unlock(&st->lock); in adf4371_write()
424 * in Hz. Using scale is a bit ugly.
466 return regmap_read(st->regmap, reg, readval); in adf4371_reg_access()
468 return regmap_write(st->regmap, reg, writeval); in adf4371_reg_access()
482 ret = regmap_write(st->regmap, ADF4371_REG(0x0), ADF4371_RESET_CMD); in adf4371_setup()
486 ret = regmap_multi_reg_write(st->regmap, adf4371_reg_defaults, in adf4371_setup()
492 if (device_property_read_bool(&st->spi->dev, "adi,mute-till-lock-en")) { in adf4371_setup()
493 ret = regmap_update_bits(st->regmap, ADF4371_REG(0x25), in adf4371_setup()
501 ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0), in adf4371_setup()
514 st->ref_div_factor++; in adf4371_setup()
515 st->fpfd = st->clkin_freq / st->ref_div_factor; in adf4371_setup()
516 } while (st->fpfd > ADF4371_MAX_FREQ_PFD); in adf4371_setup()
519 vco_band_div = DIV_ROUND_UP(st->fpfd, 2400000U); in adf4371_setup()
521 tmp = DIV_ROUND_CLOSEST(st->fpfd, 1000000U); in adf4371_setup()
532 } while (vco_alc_timeout * 1024 - timeout <= 50 * tmp); in adf4371_setup()
534 st->buf[0] = vco_band_div; in adf4371_setup()
535 st->buf[1] = timeout & 0xFF; in adf4371_setup()
536 st->buf[2] = ADF4371_TIMEOUT(timeout >> 8) | 0x04; in adf4371_setup()
537 st->buf[3] = synth_timeout; in adf4371_setup()
538 st->buf[4] = ADF4371_VCO_ALC_TOUT(vco_alc_timeout); in adf4371_setup()
540 return regmap_bulk_write(st->regmap, ADF4371_REG(0x30), st->buf, 5); in adf4371_setup()
551 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); in adf4371_probe()
553 return -ENOMEM; in adf4371_probe()
557 dev_err(&spi->dev, "Error initializing spi regmap: %ld\n", in adf4371_probe()
564 st->spi = spi; in adf4371_probe()
565 st->regmap = regmap; in adf4371_probe()
566 mutex_init(&st->lock); in adf4371_probe()
568 st->chip_info = &adf4371_chip_info[id->driver_data]; in adf4371_probe()
569 indio_dev->name = id->name; in adf4371_probe()
570 indio_dev->info = &adf4371_info; in adf4371_probe()
571 indio_dev->modes = INDIO_DIRECT_MODE; in adf4371_probe()
572 indio_dev->channels = st->chip_info->channels; in adf4371_probe()
573 indio_dev->num_channels = st->chip_info->num_channels; in adf4371_probe()
575 st->clkin = devm_clk_get_enabled(&spi->dev, "clkin"); in adf4371_probe()
576 if (IS_ERR(st->clkin)) in adf4371_probe()
577 return PTR_ERR(st->clkin); in adf4371_probe()
579 st->clkin_freq = clk_get_rate(st->clkin); in adf4371_probe()
583 dev_err(&spi->dev, "ADF4371 setup failed\n"); in adf4371_probe()
587 return devm_iio_device_register(&spi->dev, indio_dev); in adf4371_probe()