Lines Matching +full:phase +full:- +full:locked
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright 2016-2024 Analog Devices Inc.
26 #include <linux/fpga/adi-axi-common.h>
28 #include <linux/iio/buffer-dmaengine.h>
91 guard(mutex)(&st->lock); in axi_dac_enable()
92 ret = regmap_set_bits(st->regmap, AXI_DAC_REG_RSTN, in axi_dac_enable()
97 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all in axi_dac_enable()
101 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS, __val, in axi_dac_enable()
106 return regmap_set_bits(st->regmap, AXI_DAC_REG_RSTN, in axi_dac_enable()
114 guard(mutex)(&st->lock); in axi_dac_disable()
115 regmap_write(st->regmap, AXI_DAC_REG_RSTN, 0); in axi_dac_disable()
124 if (device_property_read_string(st->dev, "dma-names", &dma_name)) in axi_dac_request_buffer()
127 return iio_dmaengine_buffer_setup_ext(st->dev, indio_dev, dma_name, in axi_dac_request_buffer()
152 if (!st->dac_clk) { in __axi_dac_frequency_get()
153 dev_err(st->dev, "Sampling rate is 0...\n"); in __axi_dac_frequency_get()
154 return -EINVAL; in __axi_dac_frequency_get()
162 ret = regmap_read(st->regmap, reg, &raw); in __axi_dac_frequency_get()
167 *freq = DIV_ROUND_CLOSEST_ULL(raw * st->dac_clk, BIT(16)); in __axi_dac_frequency_get()
179 scoped_guard(mutex, &st->lock) { in axi_dac_frequency_get()
180 ret = __axi_dac_frequency_get(st, chan->channel, tone_2, &freq); in axi_dac_frequency_get()
197 reg = AXI_DAC_REG_CHAN_CNTRL_3(chan->channel); in axi_dac_scale_get()
199 reg = AXI_DAC_REG_CHAN_CNTRL_1(chan->channel); in axi_dac_scale_get()
201 ret = regmap_read(st->regmap, reg, &raw); in axi_dac_scale_get()
213 vals[0] *= -1; in axi_dac_scale_get()
215 vals[1] *= -1; in axi_dac_scale_get()
226 u32 reg, raw, phase; in axi_dac_phase_get() local
230 reg = AXI_DAC_REG_CHAN_CNTRL_4(chan->channel); in axi_dac_phase_get()
232 reg = AXI_DAC_REG_CHAN_CNTRL_2(chan->channel); in axi_dac_phase_get()
234 ret = regmap_read(st->regmap, reg, &raw); in axi_dac_phase_get()
239 phase = DIV_ROUND_CLOSEST_ULL((u64)raw * AXI_DAC_2_PI_MEGA, U16_MAX); in axi_dac_phase_get()
241 vals[0] = phase / MEGA; in axi_dac_phase_get()
242 vals[1] = phase % MEGA; in axi_dac_phase_get()
257 dev_err(st->dev, "Invalid frequency(%u) dac_clk(%llu)\n", in __axi_dac_frequency_set()
259 return -EINVAL; in __axi_dac_frequency_set()
269 ret = regmap_update_bits(st->regmap, reg, AXI_DAC_FREQUENCY, raw); in __axi_dac_frequency_set()
274 return regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_1, AXI_DAC_SYNC); in __axi_dac_frequency_set()
288 guard(mutex)(&st->lock); in axi_dac_frequency_set()
289 ret = __axi_dac_frequency_set(st, chan->channel, st->dac_clk, freq, in axi_dac_frequency_set()
310 if (scale <= -2 * (int)MEGA || scale >= 2 * (int)MEGA) in axi_dac_scale_set()
311 return -EINVAL; in axi_dac_scale_set()
316 scale *= -1; in axi_dac_scale_set()
322 reg = AXI_DAC_REG_CHAN_CNTRL_3(chan->channel); in axi_dac_scale_set()
324 reg = AXI_DAC_REG_CHAN_CNTRL_1(chan->channel); in axi_dac_scale_set()
326 guard(mutex)(&st->lock); in axi_dac_scale_set()
327 ret = regmap_write(st->regmap, reg, raw); in axi_dac_scale_set()
332 ret = regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_1, AXI_DAC_SYNC); in axi_dac_scale_set()
343 int integer, frac, phase; in axi_dac_phase_set() local
351 phase = integer * MEGA + frac; in axi_dac_phase_set()
352 if (phase < 0 || phase > AXI_DAC_2_PI_MEGA) in axi_dac_phase_set()
353 return -EINVAL; in axi_dac_phase_set()
355 raw = DIV_ROUND_CLOSEST_ULL((u64)phase * U16_MAX, AXI_DAC_2_PI_MEGA); in axi_dac_phase_set()
358 reg = AXI_DAC_REG_CHAN_CNTRL_4(chan->channel); in axi_dac_phase_set()
360 reg = AXI_DAC_REG_CHAN_CNTRL_2(chan->channel); in axi_dac_phase_set()
362 guard(mutex)(&st->lock); in axi_dac_phase_set()
363 ret = regmap_update_bits(st->regmap, reg, AXI_DAC_PHASE, in axi_dac_phase_set()
369 ret = regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_1, AXI_DAC_SYNC); in axi_dac_phase_set()
396 return -EOPNOTSUPP; in axi_dac_ext_info_set()
409 private - AXI_DAC_FREQ_TONE_1); in axi_dac_ext_info_get()
413 private - AXI_DAC_SCALE_TONE_1); in axi_dac_ext_info_get()
417 private - AXI_DAC_PHASE_TONE_1); in axi_dac_ext_info_get()
419 return -EOPNOTSUPP; in axi_dac_ext_info_get()
438 if (chan->type != IIO_ALTVOLTAGE) in axi_dac_extend_chan()
439 return -EINVAL; in axi_dac_extend_chan()
440 if (st->reg_config & AXI_DDS_DISABLE) in axi_dac_extend_chan()
444 chan->ext_info = axi_dac_ext_info; in axi_dac_extend_chan()
456 return regmap_update_bits(st->regmap, in axi_dac_data_source_set()
461 return regmap_update_bits(st->regmap, in axi_dac_data_source_set()
465 return -EINVAL; in axi_dac_data_source_set()
477 return -EINVAL; in axi_dac_set_sample_rate()
478 if (st->reg_config & AXI_DDS_DISABLE) in axi_dac_set_sample_rate()
482 guard(mutex)(&st->lock); in axi_dac_set_sample_rate()
490 if (!st->dac_clk) { in axi_dac_set_sample_rate()
491 st->dac_clk = sample_rate; in axi_dac_set_sample_rate()
505 st->dac_clk = sample_rate; in axi_dac_set_sample_rate()
516 return regmap_read(st->regmap, reg, readval); in axi_dac_reg_access()
518 return regmap_write(st->regmap, reg, writeval); in axi_dac_reg_access()
535 .name = "axi-dac",
555 st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL); in axi_dac_probe()
557 return -ENOMEM; in axi_dac_probe()
559 expected_ver = device_get_match_data(&pdev->dev); in axi_dac_probe()
561 return -ENODEV; in axi_dac_probe()
563 clk = devm_clk_get_enabled(&pdev->dev, NULL); in axi_dac_probe()
565 return dev_err_probe(&pdev->dev, PTR_ERR(clk), in axi_dac_probe()
572 st->dev = &pdev->dev; in axi_dac_probe()
573 st->regmap = devm_regmap_init_mmio(&pdev->dev, base, in axi_dac_probe()
575 if (IS_ERR(st->regmap)) in axi_dac_probe()
576 return dev_err_probe(&pdev->dev, PTR_ERR(st->regmap), in axi_dac_probe()
583 ret = regmap_write(st->regmap, AXI_DAC_REG_RSTN, 0); in axi_dac_probe()
587 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver); in axi_dac_probe()
592 dev_err(&pdev->dev, in axi_dac_probe()
600 return -ENODEV; in axi_dac_probe()
604 ret = regmap_read(st->regmap, AXI_DAC_REG_CONFIG, &st->reg_config); in axi_dac_probe()
612 * Multiple-Input and Multiple-Output (MIMO). As most of the times we in axi_dac_probe()
616 ret = regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_2, ADI_DAC_R1_MODE); in axi_dac_probe()
620 mutex_init(&st->lock); in axi_dac_probe()
621 ret = devm_iio_backend_register(&pdev->dev, &axi_dac_generic, st); in axi_dac_probe()
623 return dev_err_probe(&pdev->dev, ret, in axi_dac_probe()
626 dev_info(&pdev->dev, "AXI DAC IP core (%d.%.2d.%c) probed\n", in axi_dac_probe()
637 { .compatible = "adi,axi-dac-9.1.b", .data = &axi_dac_9_1_b_info },
644 .name = "adi-axi-dac",