Lines Matching +full:1 +full:st
37 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
60 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
61 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
79 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
90 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
109 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
133 #define AD7194_CH_POS(x) (((x) - 1) << 4)
134 #define AD7194_CH_NEG(x) ((x) - 1)
142 #define AD7194_CH_AIN_START 1
160 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
167 #define AD7192_NO_SYNC_FILTER 1
231 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_set_syscalib_mode() local
233 st->syscalib_mode[chan->channel] = mode; in ad7192_set_syscalib_mode()
241 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_get_syscalib_mode() local
243 return st->syscalib_mode[chan->channel]; in ad7192_get_syscalib_mode()
251 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_write_syscalib() local
259 temp = st->syscalib_mode[chan->channel]; in ad7192_write_syscalib()
262 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, in ad7192_write_syscalib()
265 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, in ad7192_write_syscalib()
299 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_set_channel() local
301 st->conf &= ~AD7192_CONF_CHAN_MASK; in ad7192_set_channel()
302 st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel); in ad7192_set_channel()
304 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_channel()
310 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_set_mode() local
312 st->mode &= ~AD7192_MODE_SEL_MASK; in ad7192_set_mode()
313 st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode); in ad7192_set_mode()
315 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_mode()
320 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_append_status() local
321 unsigned int mode = st->mode; in ad7192_append_status()
327 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode); in ad7192_append_status()
331 st->mode = mode; in ad7192_append_status()
338 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_disable_all() local
339 u32 conf = st->conf; in ad7192_disable_all()
344 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); in ad7192_disable_all()
348 st->conf = conf; in ad7192_disable_all()
389 static int ad7192_calibrate_all(struct ad7192_state *st) in ad7192_calibrate_all() argument
391 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, in ad7192_calibrate_all()
403 * configuration AD7192_CLK_EXT_MCLK1_2 and position 1, mclk, corresponds to
424 struct ad7192_state *st = clk_hw_to_ad7192(hw); in ad7192_clk_output_is_enabled() local
426 return st->clock_sel == AD7192_CLK_INT_CO; in ad7192_clk_output_is_enabled()
431 struct ad7192_state *st = clk_hw_to_ad7192(hw); in ad7192_clk_prepare() local
434 st->mode &= ~AD7192_MODE_CLKSRC_MASK; in ad7192_clk_prepare()
435 st->mode |= AD7192_CLK_INT_CO; in ad7192_clk_prepare()
437 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_clk_prepare()
441 st->clock_sel = AD7192_CLK_INT_CO; in ad7192_clk_prepare()
448 struct ad7192_state *st = clk_hw_to_ad7192(hw); in ad7192_clk_unprepare() local
451 st->mode &= ~AD7192_MODE_CLKSRC_MASK; in ad7192_clk_unprepare()
452 st->mode |= AD7192_CLK_INT; in ad7192_clk_unprepare()
454 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_clk_unprepare()
458 st->clock_sel = AD7192_CLK_INT; in ad7192_clk_unprepare()
468 static int ad7192_register_clk_provider(struct ad7192_state *st) in ad7192_register_clk_provider() argument
470 struct device *dev = &st->sd.spi->dev; in ad7192_register_clk_provider()
487 st->int_clk_hw.init = &init; in ad7192_register_clk_provider()
488 ret = devm_clk_hw_register(dev, &st->int_clk_hw); in ad7192_register_clk_provider()
493 &st->int_clk_hw); in ad7192_register_clk_provider()
496 static int ad7192_clock_setup(struct ad7192_state *st) in ad7192_clock_setup() argument
498 struct device *dev = &st->sd.spi->dev; in ad7192_clock_setup()
508 st->clock_sel = AD7192_CLK_INT_CO; in ad7192_clock_setup()
509 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_clock_setup()
515 st->clock_sel = AD7192_CLK_EXT_MCLK1_2; in ad7192_clock_setup()
516 st->mclk = devm_clk_get_enabled(dev, "mclk"); in ad7192_clock_setup()
517 if (IS_ERR(st->mclk)) in ad7192_clock_setup()
518 return dev_err_probe(dev, PTR_ERR(st->mclk), in ad7192_clock_setup()
521 st->fclk = clk_get_rate(st->mclk); in ad7192_clock_setup()
522 if (!ad7192_valid_external_frequency(st->fclk)) in ad7192_clock_setup()
534 st->clock_sel = AD7192_CLK_INT; in ad7192_clock_setup()
535 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_clock_setup()
537 ret = ad7192_register_clk_provider(st); in ad7192_clock_setup()
544 st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret; in ad7192_clock_setup()
546 st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]); in ad7192_clock_setup()
547 if (IS_ERR(st->mclk)) in ad7192_clock_setup()
548 return dev_err_probe(dev, PTR_ERR(st->mclk), in ad7192_clock_setup()
551 st->fclk = clk_get_rate(st->mclk); in ad7192_clock_setup()
552 if (!ad7192_valid_external_frequency(st->fclk)) in ad7192_clock_setup()
561 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_setup() local
568 ret = ad_sd_reset(&st->sd, 48); in ad7192_setup()
574 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); in ad7192_setup()
580 if (id != st->chip_info->chip_id) in ad7192_setup()
582 id, st->chip_info->chip_id); in ad7192_setup()
584 st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) | in ad7192_setup()
585 FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) | in ad7192_setup()
588 st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0); in ad7192_setup()
592 st->mode |= AD7192_MODE_REJ60; in ad7192_setup()
595 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) in ad7192_setup()
596 st->conf |= AD7192_CONF_REFSEL; in ad7192_setup()
598 st->conf &= ~AD7192_CONF_CHOP; in ad7192_setup()
602 st->conf |= AD7192_CONF_BUF; in ad7192_setup()
606 st->conf |= AD7192_CONF_UNIPOLAR; in ad7192_setup()
611 st->conf |= AD7192_CONF_BURN; in ad7192_setup()
617 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_setup()
621 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_setup()
625 ret = ad7192_calibrate_all(st); in ad7192_setup()
630 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { in ad7192_setup()
631 scale_uv = ((u64)st->int_vref_mv * 100000000) in ad7192_setup()
633 !FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf)); in ad7192_setup()
636 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; in ad7192_setup()
637 st->scale_avail[i][0] = scale_uv; in ad7192_setup()
640 st->oversampling_ratio_avail[0] = 1; in ad7192_setup()
641 st->oversampling_ratio_avail[1] = 2; in ad7192_setup()
642 st->oversampling_ratio_avail[2] = 8; in ad7192_setup()
643 st->oversampling_ratio_avail[3] = 16; in ad7192_setup()
645 st->filter_freq_avail[0][0] = 600; in ad7192_setup()
646 st->filter_freq_avail[1][0] = 800; in ad7192_setup()
647 st->filter_freq_avail[2][0] = 2300; in ad7192_setup()
648 st->filter_freq_avail[3][0] = 2720; in ad7192_setup()
650 st->filter_freq_avail[0][1] = 1000; in ad7192_setup()
651 st->filter_freq_avail[1][1] = 1000; in ad7192_setup()
652 st->filter_freq_avail[2][1] = 1000; in ad7192_setup()
653 st->filter_freq_avail[3][1] = 1000; in ad7192_setup()
663 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_show_ac_excitation() local
665 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf)); in ad7192_show_ac_excitation()
673 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_show_bridge_switch() local
676 FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon)); in ad7192_show_bridge_switch()
685 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_set() local
701 st->gpocon |= AD7192_GPOCON_BPDSW; in ad7192_set()
703 st->gpocon &= ~AD7192_GPOCON_BPDSW; in ad7192_set()
705 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); in ad7192_set()
709 st->conf |= AD7192_CONF_ACX; in ad7192_set()
711 st->conf &= ~AD7192_CONF_ACX; in ad7192_set()
713 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set()
724 static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en) in ad7192_compute_f_order() argument
728 avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode); in ad7192_compute_f_order()
731 return 1; in ad7192_compute_f_order()
733 oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected]; in ad7192_compute_f_order()
736 return AD7192_SYNC3_FILTER + oversampling_ratio - 1; in ad7192_compute_f_order()
738 return AD7192_SYNC4_FILTER + oversampling_ratio - 1; in ad7192_compute_f_order()
741 static int ad7192_get_f_order(struct ad7192_state *st) in ad7192_get_f_order() argument
745 sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode); in ad7192_get_f_order()
746 chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf); in ad7192_get_f_order()
748 return ad7192_compute_f_order(st, sinc3_en, chop_en); in ad7192_get_f_order()
751 static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en, in ad7192_compute_f_adc() argument
754 unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en); in ad7192_compute_f_adc()
756 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_compute_f_adc()
757 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); in ad7192_compute_f_adc()
760 static int ad7192_get_f_adc(struct ad7192_state *st) in ad7192_get_f_adc() argument
762 unsigned int f_order = ad7192_get_f_order(st); in ad7192_get_f_adc()
764 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_f_adc()
765 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); in ad7192_get_f_adc()
768 static void ad7192_update_filter_freq_avail(struct ad7192_state *st) in ad7192_update_filter_freq_avail() argument
773 fadc = ad7192_compute_f_adc(st, false, true); in ad7192_update_filter_freq_avail()
774 st->filter_freq_avail[0][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); in ad7192_update_filter_freq_avail()
776 fadc = ad7192_compute_f_adc(st, true, true); in ad7192_update_filter_freq_avail()
777 st->filter_freq_avail[1][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); in ad7192_update_filter_freq_avail()
779 fadc = ad7192_compute_f_adc(st, false, false); in ad7192_update_filter_freq_avail()
780 st->filter_freq_avail[2][0] = DIV_ROUND_CLOSEST(fadc * 230, 1024); in ad7192_update_filter_freq_avail()
782 fadc = ad7192_compute_f_adc(st, true, false); in ad7192_update_filter_freq_avail()
783 st->filter_freq_avail[3][0] = DIV_ROUND_CLOSEST(fadc * 272, 1024); in ad7192_update_filter_freq_avail()
818 static int ad7192_set_3db_filter_freq(struct ad7192_state *st, in ad7192_set_3db_filter_freq() argument
828 for (i = 0; i < ARRAY_SIZE(st->filter_freq_avail); i++) { in ad7192_set_3db_filter_freq()
829 diff_new = abs(freq - st->filter_freq_avail[i][0]); in ad7192_set_3db_filter_freq()
838 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
840 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
842 case 1: in ad7192_set_3db_filter_freq()
843 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
845 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
848 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
850 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
853 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
855 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
859 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_3db_filter_freq()
863 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_3db_filter_freq()
866 static int ad7192_get_3db_filter_freq(struct ad7192_state *st) in ad7192_get_3db_filter_freq() argument
870 fadc = ad7192_get_f_adc(st); in ad7192_get_3db_filter_freq()
872 if (FIELD_GET(AD7192_CONF_CHOP, st->conf)) in ad7192_get_3db_filter_freq()
874 if (FIELD_GET(AD7192_MODE_SINC3, st->mode)) in ad7192_get_3db_filter_freq()
886 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_read_raw() local
887 bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf); in ad7192_read_raw()
888 u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf); in ad7192_read_raw()
896 mutex_lock(&st->lock); in ad7192_read_raw()
897 *val = st->scale_avail[gain][0]; in ad7192_read_raw()
898 *val2 = st->scale_avail[gain][1]; in ad7192_read_raw()
899 mutex_unlock(&st->lock); in ad7192_read_raw()
910 *val = -(1 << (chan->scan_type.realbits - 1)); in ad7192_read_raw()
920 if (st->aincom_mv && !chan->differential) in ad7192_read_raw()
921 *val += DIV_ROUND_CLOSEST_ULL((u64)st->aincom_mv * NANO, in ad7192_read_raw()
922 st->scale_avail[gain][1]); in ad7192_read_raw()
932 *val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024); in ad7192_read_raw()
935 *val = ad7192_get_3db_filter_freq(st); in ad7192_read_raw()
939 *val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)]; in ad7192_read_raw()
952 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_write_raw() local
960 mutex_lock(&st->lock); in ad7192_write_raw()
965 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) in ad7192_write_raw()
966 if (val2 == st->scale_avail[i][1]) { in ad7192_write_raw()
968 tmp = st->conf; in ad7192_write_raw()
969 st->conf &= ~AD7192_CONF_GAIN_MASK; in ad7192_write_raw()
970 st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i); in ad7192_write_raw()
971 if (tmp == st->conf) in ad7192_write_raw()
973 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, in ad7192_write_raw()
974 3, st->conf); in ad7192_write_raw()
975 ad7192_calibrate_all(st); in ad7192_write_raw()
985 div = st->fclk / (val * ad7192_get_f_order(st) * 1024); in ad7192_write_raw()
986 if (div < 1 || div > 1023) { in ad7192_write_raw()
991 st->mode &= ~AD7192_MODE_RATE_MASK; in ad7192_write_raw()
992 st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div); in ad7192_write_raw()
993 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_write_raw()
994 ad7192_update_filter_freq_avail(st); in ad7192_write_raw()
997 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000); in ad7192_write_raw()
1001 for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++) in ad7192_write_raw()
1002 if (val == st->oversampling_ratio_avail[i]) { in ad7192_write_raw()
1004 tmp = st->mode; in ad7192_write_raw()
1005 st->mode &= ~AD7192_MODE_AVG_MASK; in ad7192_write_raw()
1006 st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i); in ad7192_write_raw()
1007 if (tmp == st->mode) in ad7192_write_raw()
1009 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, in ad7192_write_raw()
1010 3, st->mode); in ad7192_write_raw()
1013 ad7192_update_filter_freq_avail(st); in ad7192_write_raw()
1019 mutex_unlock(&st->lock); in ad7192_write_raw()
1049 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_read_avail() local
1053 *vals = (int *)st->scale_avail; in ad7192_read_avail()
1056 *length = ARRAY_SIZE(st->scale_avail) * 2; in ad7192_read_avail()
1060 *vals = (int *)st->filter_freq_avail; in ad7192_read_avail()
1062 *length = ARRAY_SIZE(st->filter_freq_avail) * 2; in ad7192_read_avail()
1066 *vals = (int *)st->oversampling_ratio_avail; in ad7192_read_avail()
1068 *length = ARRAY_SIZE(st->oversampling_ratio_avail); in ad7192_read_avail()
1078 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_update_scan_mode() local
1079 u32 conf = st->conf; in ad7192_update_scan_mode()
1087 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); in ad7192_update_scan_mode()
1091 st->conf = conf; in ad7192_update_scan_mode()
1128 .differential = ((_channel2) == -1 ? 0 : 1), \
1129 .indexed = 1, \
1158 __AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \
1162 __AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL)
1173 AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address)
1176 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
1177 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
1180 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
1188 AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
1189 AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
1194 AD7193_CHANNEL(6, 1, AD7193_CH_AIN1),
1246 if (!ad7194_validate_ain_channel(dev, ain[1])) in ad7194_parse_channels()
1249 ain[1]); in ad7194_parse_channels()
1254 ad7194_channels->channel2 = ain[1]; in ad7194_parse_channels()
1255 ad7194_channels->address = AD7194_DIFF_CH(ain[0], ain[1]); in ad7194_parse_channels()
1332 struct ad7192_state *st; in ad7192_probe() local
1339 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); in ad7192_probe()
1343 st = iio_priv(indio_dev); in ad7192_probe()
1345 mutex_init(&st->lock); in ad7192_probe()
1356 st->aincom_mv = ret == -ENODEV ? 0 : ret / MILLI; in ad7192_probe()
1394 st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI; in ad7192_probe()
1396 st->chip_info = spi_get_device_match_data(spi); in ad7192_probe()
1397 indio_dev->name = st->chip_info->name; in ad7192_probe()
1399 indio_dev->info = st->chip_info->info; in ad7192_probe()
1400 if (st->chip_info->parse_channels) { in ad7192_probe()
1401 ret = st->chip_info->parse_channels(indio_dev); in ad7192_probe()
1405 indio_dev->channels = st->chip_info->channels; in ad7192_probe()
1406 indio_dev->num_channels = st->chip_info->num_channels; in ad7192_probe()
1409 ret = ad_sd_init(&st->sd, indio_dev, spi, st->chip_info->sigma_delta_info); in ad7192_probe()
1417 ret = ad7192_clock_setup(st); in ad7192_probe()