1 // SPDX-License-Identifier: BSD-3-Clause
24 static int hci_extcap_hardware_id(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_hardware_id()  argument
26 	hci->vendor_mipi_id	= readl(base + 0x04);  in hci_extcap_hardware_id()
27 	hci->vendor_version_id	= readl(base + 0x08);  in hci_extcap_hardware_id()
28 	hci->vendor_product_id	= readl(base + 0x0c);  in hci_extcap_hardware_id()
30 	dev_info(&hci->master.dev, "vendor MIPI ID: %#x\n", hci->vendor_mipi_id);  in hci_extcap_hardware_id()
31 	dev_info(&hci->master.dev, "vendor version ID: %#x\n", hci->vendor_version_id);  in hci_extcap_hardware_id()
32 	dev_info(&hci->master.dev, "vendor product ID: %#x\n", hci->vendor_product_id);  in hci_extcap_hardware_id()
35 	switch (hci->vendor_mipi_id) {  in hci_extcap_hardware_id()
37 		hci->quirks |= HCI_QUIRK_RAW_CCC;  in hci_extcap_hardware_id()
45 static int hci_extcap_master_config(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_master_config()  argument
47 	u32 master_config = readl(base + 0x04);  in hci_extcap_master_config()
52 	dev_info(&hci->master.dev, "operation mode: %s\n", functionality[operation_mode]);  in hci_extcap_master_config()
55 	dev_err(&hci->master.dev, "only master mode is currently supported\n");  in hci_extcap_master_config()
56 	return -EOPNOTSUPP;  in hci_extcap_master_config()
59 static int hci_extcap_multi_bus(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_multi_bus()  argument
61 	u32 bus_instance = readl(base + 0x04);  in hci_extcap_multi_bus()
62 	unsigned int count = FIELD_GET(GENMASK(3, 0), bus_instance);  in hci_extcap_multi_bus()
64 	dev_info(&hci->master.dev, "%d bus instances\n", count);  in hci_extcap_multi_bus()
68 static int hci_extcap_xfer_modes(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_xfer_modes()  argument
70 	u32 header = readl(base);  in hci_extcap_xfer_modes()
71 	u32 entries = FIELD_GET(CAP_HEADER_LENGTH, header) - 1;  in hci_extcap_xfer_modes()
74 	dev_info(&hci->master.dev, "transfer mode table has %d entries\n",  in hci_extcap_xfer_modes()
76 	base += 4;  /* skip header */  in hci_extcap_xfer_modes()
78 		u32 mode_entry = readl(base);  in hci_extcap_xfer_modes()
80 		DBG("mode %d: 0x%08x", index, mode_entry);  in hci_extcap_xfer_modes()
82 		base += 4;  in hci_extcap_xfer_modes()
88 static int hci_extcap_xfer_rates(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_xfer_rates()  argument
90 	u32 header = readl(base);  in hci_extcap_xfer_rates()
91 	u32 entries = FIELD_GET(CAP_HEADER_LENGTH, header) - 1;  in hci_extcap_xfer_rates()
95 	base += 4;  /* skip header */  in hci_extcap_xfer_rates()
97 	dev_info(&hci->master.dev, "available data rates:\n");  in hci_extcap_xfer_rates()
99 		rate_entry = readl(base);  in hci_extcap_xfer_rates()
100 		DBG("entry %d: 0x%08x", index, rate_entry);  in hci_extcap_xfer_rates()
104 		dev_info(&hci->master.dev, "rate %d for %s = %d kHz\n",  in hci_extcap_xfer_rates()
110 		base += 4;  in hci_extcap_xfer_rates()
116 static int hci_extcap_auto_command(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_auto_command()  argument
118 	u32 autocmd_ext_caps = readl(base + 0x04);  in hci_extcap_auto_command()
119 	unsigned int max_count = FIELD_GET(GENMASK(3, 0), autocmd_ext_caps);  in hci_extcap_auto_command()
120 	u32 autocmd_ext_config = readl(base + 0x08);  in hci_extcap_auto_command()
121 	unsigned int count = FIELD_GET(GENMASK(3, 0), autocmd_ext_config);  in hci_extcap_auto_command()
123 	dev_info(&hci->master.dev, "%d/%d active auto-command entries\n",  in hci_extcap_auto_command()
125 	/* remember auto-command register location for later use */  in hci_extcap_auto_command()
126 	hci->AUTOCMD_regs = base;  in hci_extcap_auto_command()
130 static int hci_extcap_debug(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_debug()  argument
132 	dev_info(&hci->master.dev, "debug registers present\n");  in hci_extcap_debug()
133 	hci->DEBUG_regs = base;  in hci_extcap_debug()
137 static int hci_extcap_scheduled_cmd(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_scheduled_cmd()  argument
139 	dev_info(&hci->master.dev, "scheduled commands available\n");  in hci_extcap_scheduled_cmd()
140 	/* hci->schedcmd_regs = base; */  in hci_extcap_scheduled_cmd()
144 static int hci_extcap_non_curr_master(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_non_curr_master()  argument
146 	dev_info(&hci->master.dev, "Non-Current Master support available\n");  in hci_extcap_non_curr_master()
147 	/* hci->NCM_regs = base; */  in hci_extcap_non_curr_master()
151 static int hci_extcap_ccc_resp_conf(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_ccc_resp_conf()  argument
153 	dev_info(&hci->master.dev, "CCC Response Configuration available\n");  in hci_extcap_ccc_resp_conf()
157 static int hci_extcap_global_DAT(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_global_DAT()  argument
159 	dev_info(&hci->master.dev, "Global DAT available\n");  in hci_extcap_global_DAT()
163 static int hci_extcap_multilane(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_multilane()  argument
165 	dev_info(&hci->master.dev, "Master Multi-Lane support available\n");  in hci_extcap_multilane()
169 static int hci_extcap_ncm_multilane(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_ncm_multilane()  argument
171 	dev_info(&hci->master.dev, "NCM Multi-Lane support available\n");  in hci_extcap_ncm_multilane()
178 	int (*parser)(struct i3c_hci *hci, void __iomem *base);
201 static int hci_extcap_vendor_NXP(struct i3c_hci *hci, void __iomem *base)  in hci_extcap_vendor_NXP()  argument
203 	hci->vendor_data = (__force void *)base;  in hci_extcap_vendor_NXP()
204 	dev_info(&hci->master.dev, "Build Date Info = %#x\n", readl(base + 1*4));  in hci_extcap_vendor_NXP()
206 	writel(0xdeadbeef, base + 1*4);  in hci_extcap_vendor_NXP()
214 	int (*parser)(struct i3c_hci *hci, void __iomem *base);
226 static int hci_extcap_vendor_specific(struct i3c_hci *hci, void __iomem *base,  in hci_extcap_vendor_specific()  argument
234 		if (vendor_ext_caps[i].vendor == hci->vendor_mipi_id &&  in hci_extcap_vendor_specific()
242 		dev_notice(&hci->master.dev,  in hci_extcap_vendor_specific()
243 			   "unknown ext_cap 0x%02x for vendor 0x%02x\n",  in hci_extcap_vendor_specific()
244 			   cap_id, hci->vendor_mipi_id);  in hci_extcap_vendor_specific()
247 	if (cap_length < vendor_cap_entry->min_length) {  in hci_extcap_vendor_specific()
248 		dev_err(&hci->master.dev,  in hci_extcap_vendor_specific()
249 			"ext_cap 0x%02x has size %d (expecting >= %d)\n",  in hci_extcap_vendor_specific()
250 			cap_id, cap_length, vendor_cap_entry->min_length);  in hci_extcap_vendor_specific()
251 		return -EINVAL;  in hci_extcap_vendor_specific()
253 	return vendor_cap_entry->parser(hci, base);  in hci_extcap_vendor_specific()
258 	void __iomem *curr_cap = hci->EXTCAPS_regs;  in i3c_hci_parse_ext_caps()
271 		DBG("id=0x%02x length=%d", cap_id, cap_length);  in i3c_hci_parse_ext_caps()
275 			dev_err(&hci->master.dev,  in i3c_hci_parse_ext_caps()
276 				"ext_cap 0x%02x has size %d (too big)\n",  in i3c_hci_parse_ext_caps()
278 			err = -EINVAL;  in i3c_hci_parse_ext_caps()
296 			dev_notice(&hci->master.dev,  in i3c_hci_parse_ext_caps()
297 				   "unknown ext_cap 0x%02x\n", cap_id);  in i3c_hci_parse_ext_caps()
298 		} else if (cap_length < cap_entry->min_length) {  in i3c_hci_parse_ext_caps()
299 			dev_err(&hci->master.dev,  in i3c_hci_parse_ext_caps()
300 				"ext_cap 0x%02x has size %d (expecting >= %d)\n",  in i3c_hci_parse_ext_caps()
301 				cap_id, cap_length, cap_entry->min_length);  in i3c_hci_parse_ext_caps()
302 			err = -EINVAL;  in i3c_hci_parse_ext_caps()
304 			err = cap_entry->parser(hci, curr_cap);  in i3c_hci_parse_ext_caps()