Lines Matching refs:hci
122 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_bus_init() local
128 if (hci->cmd == &mipi_i3c_hci_cmd_v1) { in i3c_hci_bus_init()
129 ret = mipi_i3c_hci_dat_v1.init(hci); in i3c_hci_bus_init()
145 ret = hci->io->init(hci); in i3c_hci_bus_init()
150 if (hci->quirks & HCI_QUIRK_RESP_BUF_THLD) in i3c_hci_bus_init()
151 amd_set_resp_buf_thld(hci); in i3c_hci_bus_init()
161 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_bus_cleanup() local
168 hci->io->cleanup(hci); in i3c_hci_bus_cleanup()
169 if (hci->cmd == &mipi_i3c_hci_cmd_v1) in i3c_hci_bus_cleanup()
170 mipi_i3c_hci_dat_v1.cleanup(hci); in i3c_hci_bus_cleanup()
173 void mipi_i3c_hci_resume(struct i3c_hci *hci) in mipi_i3c_hci_resume() argument
179 void mipi_i3c_hci_pio_reset(struct i3c_hci *hci) in mipi_i3c_hci_pio_reset() argument
185 void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci) in mipi_i3c_hci_dct_index_reset() argument
193 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_send_ccc_cmd() local
195 bool raw = !!(hci->quirks & HCI_QUIRK_RAW_CCC); in i3c_hci_send_ccc_cmd()
212 hci->cmd->prep_ccc(hci, xfer, I3C_BROADCAST_ADDR, in i3c_hci_send_ccc_cmd()
221 ret = hci->cmd->prep_ccc(hci, &xfer[i], ccc->dests[i].addr, in i3c_hci_send_ccc_cmd()
234 ret = hci->io->queue_xfer(hci, xfer, nxfers); in i3c_hci_send_ccc_cmd()
238 hci->io->dequeue_xfer(hci, xfer, nxfers)) { in i3c_hci_send_ccc_cmd()
270 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_daa() local
274 return hci->cmd->perform_daa(hci); in i3c_hci_daa()
277 static int i3c_hci_alloc_safe_xfer_buf(struct i3c_hci *hci, in i3c_hci_alloc_safe_xfer_buf() argument
280 if (hci->io != &mipi_i3c_hci_dma || in i3c_hci_alloc_safe_xfer_buf()
293 static void i3c_hci_free_safe_xfer_buf(struct i3c_hci *hci, in i3c_hci_free_safe_xfer_buf() argument
296 if (hci->io != &mipi_i3c_hci_dma || xfer->bounce_buf == NULL) in i3c_hci_free_safe_xfer_buf()
310 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_priv_xfers() local
322 size_limit = 1U << (16 + FIELD_GET(HC_CAP_MAX_DATA_LENGTH, hci->caps)); in i3c_hci_priv_xfers()
336 hci->cmd->prep_i3c_xfer(hci, dev, &xfer[i]); in i3c_hci_priv_xfers()
338 ret = i3c_hci_alloc_safe_xfer_buf(hci, &xfer[i]); in i3c_hci_priv_xfers()
346 ret = hci->io->queue_xfer(hci, xfer, nxfers); in i3c_hci_priv_xfers()
350 hci->io->dequeue_xfer(hci, xfer, nxfers)) { in i3c_hci_priv_xfers()
365 i3c_hci_free_safe_xfer_buf(hci, &xfer[i]); in i3c_hci_priv_xfers()
375 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_i2c_xfers() local
390 hci->cmd->prep_i2c_xfer(hci, dev, &xfer[i]); in i3c_hci_i2c_xfers()
392 ret = i3c_hci_alloc_safe_xfer_buf(hci, &xfer[i]); in i3c_hci_i2c_xfers()
400 ret = hci->io->queue_xfer(hci, xfer, nxfers); in i3c_hci_i2c_xfers()
404 hci->io->dequeue_xfer(hci, xfer, nxfers)) { in i3c_hci_i2c_xfers()
417 i3c_hci_free_safe_xfer_buf(hci, &xfer[i]); in i3c_hci_i2c_xfers()
426 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_attach_i3c_dev() local
435 if (hci->cmd == &mipi_i3c_hci_cmd_v1) { in i3c_hci_attach_i3c_dev()
436 ret = mipi_i3c_hci_dat_v1.alloc_entry(hci); in i3c_hci_attach_i3c_dev()
441 mipi_i3c_hci_dat_v1.set_dynamic_addr(hci, ret, dev->info.dyn_addr); in i3c_hci_attach_i3c_dev()
451 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_reattach_i3c_dev() local
456 if (hci->cmd == &mipi_i3c_hci_cmd_v1) in i3c_hci_reattach_i3c_dev()
457 mipi_i3c_hci_dat_v1.set_dynamic_addr(hci, dev_data->dat_idx, in i3c_hci_reattach_i3c_dev()
465 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_detach_i3c_dev() local
471 if (hci->cmd == &mipi_i3c_hci_cmd_v1) in i3c_hci_detach_i3c_dev()
472 mipi_i3c_hci_dat_v1.free_entry(hci, dev_data->dat_idx); in i3c_hci_detach_i3c_dev()
479 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_attach_i2c_dev() local
485 if (hci->cmd != &mipi_i3c_hci_cmd_v1) in i3c_hci_attach_i2c_dev()
490 ret = mipi_i3c_hci_dat_v1.alloc_entry(hci); in i3c_hci_attach_i2c_dev()
495 mipi_i3c_hci_dat_v1.set_static_addr(hci, ret, dev->addr); in i3c_hci_attach_i2c_dev()
496 mipi_i3c_hci_dat_v1.set_flags(hci, ret, DAT_0_I2C_DEVICE, 0); in i3c_hci_attach_i2c_dev()
505 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_detach_i2c_dev() local
512 if (hci->cmd == &mipi_i3c_hci_cmd_v1) in i3c_hci_detach_i2c_dev()
513 mipi_i3c_hci_dat_v1.free_entry(hci, dev_data->dat_idx); in i3c_hci_detach_i2c_dev()
522 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_request_ibi() local
527 mipi_i3c_hci_dat_v1.set_flags(hci, dat_idx, DAT_0_IBI_PAYLOAD, 0); in i3c_hci_request_ibi()
529 mipi_i3c_hci_dat_v1.clear_flags(hci, dat_idx, DAT_0_IBI_PAYLOAD, 0); in i3c_hci_request_ibi()
530 return hci->io->request_ibi(hci, dev, req); in i3c_hci_request_ibi()
536 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_free_ibi() local
538 hci->io->free_ibi(hci, dev); in i3c_hci_free_ibi()
544 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_enable_ibi() local
547 mipi_i3c_hci_dat_v1.clear_flags(hci, dev_data->dat_idx, DAT_0_SIR_REJECT, 0); in i3c_hci_enable_ibi()
554 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_disable_ibi() local
557 mipi_i3c_hci_dat_v1.set_flags(hci, dev_data->dat_idx, DAT_0_SIR_REJECT, 0); in i3c_hci_disable_ibi()
565 struct i3c_hci *hci = to_i3c_hci(m); in i3c_hci_recycle_ibi_slot() local
567 hci->io->recycle_ibi_slot(hci, dev, slot); in i3c_hci_recycle_ibi_slot()
591 struct i3c_hci *hci = dev_id; in i3c_hci_irq_handler() local
610 dev_err(&hci->master.dev, "Host Controller Internal Error\n"); in i3c_hci_irq_handler()
614 hci->io->irq_handler(hci, 0); in i3c_hci_irq_handler()
618 hci->io->irq_handler(hci, val & INTR_HC_RINGS); in i3c_hci_irq_handler()
622 dev_err(&hci->master.dev, "unexpected INTR_STATUS %#x\n", val); in i3c_hci_irq_handler()
629 static int i3c_hci_init(struct i3c_hci *hci) in i3c_hci_init() argument
637 hci->version_major = (regval >> 8) & 0xf; in i3c_hci_init()
638 hci->version_minor = (regval >> 4) & 0xf; in i3c_hci_init()
639 hci->revision = regval & 0xf; in i3c_hci_init()
640 dev_notice(&hci->master.dev, "MIPI I3C HCI v%u.%u r%02u\n", in i3c_hci_init()
641 hci->version_major, hci->version_minor, hci->revision); in i3c_hci_init()
649 dev_err(&hci->master.dev, "unsupported HCI version\n"); in i3c_hci_init()
653 hci->caps = reg_read(HC_CAPABILITIES); in i3c_hci_init()
654 DBG("caps = %#x", hci->caps); in i3c_hci_init()
656 size_in_dwords = hci->version_major < 1 || in i3c_hci_init()
657 (hci->version_major == 1 && hci->version_minor < 1); in i3c_hci_init()
661 hci->DAT_regs = offset ? hci->base_regs + offset : NULL; in i3c_hci_init()
662 hci->DAT_entries = FIELD_GET(DAT_TABLE_SIZE, regval); in i3c_hci_init()
663 hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8; in i3c_hci_init()
665 hci->DAT_entries = 4 * hci->DAT_entries / hci->DAT_entry_size; in i3c_hci_init()
666 dev_info(&hci->master.dev, "DAT: %u %u-bytes entries at offset %#x\n", in i3c_hci_init()
667 hci->DAT_entries, hci->DAT_entry_size, offset); in i3c_hci_init()
671 hci->DCT_regs = offset ? hci->base_regs + offset : NULL; in i3c_hci_init()
672 hci->DCT_entries = FIELD_GET(DCT_TABLE_SIZE, regval); in i3c_hci_init()
673 hci->DCT_entry_size = FIELD_GET(DCT_ENTRY_SIZE, regval) ? 0 : 16; in i3c_hci_init()
675 hci->DCT_entries = 4 * hci->DCT_entries / hci->DCT_entry_size; in i3c_hci_init()
676 dev_info(&hci->master.dev, "DCT: %u %u-bytes entries at offset %#x\n", in i3c_hci_init()
677 hci->DCT_entries, hci->DCT_entry_size, offset); in i3c_hci_init()
681 hci->RHS_regs = offset ? hci->base_regs + offset : NULL; in i3c_hci_init()
682 dev_info(&hci->master.dev, "Ring Headers at offset %#x\n", offset); in i3c_hci_init()
686 hci->PIO_regs = offset ? hci->base_regs + offset : NULL; in i3c_hci_init()
687 dev_info(&hci->master.dev, "PIO section at offset %#x\n", offset); in i3c_hci_init()
691 hci->EXTCAPS_regs = offset ? hci->base_regs + offset : NULL; in i3c_hci_init()
692 dev_info(&hci->master.dev, "Extended Caps at offset %#x\n", offset); in i3c_hci_init()
694 ret = i3c_hci_parse_ext_caps(hci); in i3c_hci_init()
725 dev_err(&hci->master.dev, "cannot set BE mode\n"); in i3c_hci_init()
735 dev_err(&hci->master.dev, "cannot clear BE mode\n"); in i3c_hci_init()
742 switch (FIELD_GET(HC_CAP_CMD_SIZE, hci->caps)) { in i3c_hci_init()
744 hci->cmd = &mipi_i3c_hci_cmd_v1; in i3c_hci_init()
747 hci->cmd = &mipi_i3c_hci_cmd_v2; in i3c_hci_init()
750 dev_err(&hci->master.dev, "wrong CMD_SIZE capability value\n"); in i3c_hci_init()
754 mode_selector = hci->version_major > 1 || in i3c_hci_init()
755 (hci->version_major == 1 && hci->version_minor > 0); in i3c_hci_init()
758 if (hci->quirks & HCI_QUIRK_PIO_MODE) in i3c_hci_init()
759 hci->RHS_regs = NULL; in i3c_hci_init()
762 if (hci->RHS_regs) { in i3c_hci_init()
765 dev_err(&hci->master.dev, "PIO mode is stuck\n"); in i3c_hci_init()
768 hci->io = &mipi_i3c_hci_dma; in i3c_hci_init()
769 dev_info(&hci->master.dev, "Using DMA\n"); in i3c_hci_init()
774 if (!hci->io && hci->PIO_regs) { in i3c_hci_init()
777 dev_err(&hci->master.dev, "DMA mode is stuck\n"); in i3c_hci_init()
780 hci->io = &mipi_i3c_hci_pio; in i3c_hci_init()
781 dev_info(&hci->master.dev, "Using PIO\n"); in i3c_hci_init()
785 if (!hci->io) { in i3c_hci_init()
786 dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n"); in i3c_hci_init()
793 if (hci->quirks & HCI_QUIRK_OD_PP_TIMING) in i3c_hci_init()
794 amd_set_od_pp_timing(hci); in i3c_hci_init()
801 struct i3c_hci *hci; in i3c_hci_probe() local
804 hci = devm_kzalloc(&pdev->dev, sizeof(*hci), GFP_KERNEL); in i3c_hci_probe()
805 if (!hci) in i3c_hci_probe()
807 hci->base_regs = devm_platform_ioremap_resource(pdev, 0); in i3c_hci_probe()
808 if (IS_ERR(hci->base_regs)) in i3c_hci_probe()
809 return PTR_ERR(hci->base_regs); in i3c_hci_probe()
811 platform_set_drvdata(pdev, hci); in i3c_hci_probe()
813 hci->master.dev.init_name = dev_name(&pdev->dev); in i3c_hci_probe()
815 hci->quirks = (unsigned long)device_get_match_data(&pdev->dev); in i3c_hci_probe()
817 ret = i3c_hci_init(hci); in i3c_hci_probe()
823 0, NULL, hci); in i3c_hci_probe()
827 ret = i3c_master_register(&hci->master, &pdev->dev, in i3c_hci_probe()
837 struct i3c_hci *hci = platform_get_drvdata(pdev); in i3c_hci_remove() local
839 i3c_master_unregister(&hci->master); in i3c_hci_remove()