276 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)  in xiic_setreg32()  function
299 	xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);  in xiic_irq_dis()
306 	xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);  in xiic_irq_en()
313 	xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);  in xiic_irq_clr()
414 	xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1);  in xiic_setclk()
417 	xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1);  in xiic_setclk()
421 	xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1);  in xiic_setclk()
425 	xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1);  in xiic_setclk()
429 	xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1);  in xiic_setclk()
433 	xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1);  in xiic_setclk()
437 	xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1);  in xiic_setclk()
440 	xiic_setreg32(i2c, XIIC_THDDAT_REG_OFFSET, 1);  in xiic_setclk()
449 	xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);  in xiic_reinit()
470 	xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);  in xiic_reinit()
481 	xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);  in xiic_deinit()
827 	xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);  in xiic_process()
983 	xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);  in xiic_start_recv()
1309 	xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);  in xiic_i2c_probe()