Lines Matching full:i2c
3 * i2c-xiic.c
24 #include <linux/i2c.h>
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
56 * struct xiic_i2c - Internal representation of the XIIC I2C bus
75 * @input_clk: Input clock to I2C controller
76 * @i2c_clk: I2C SCL frequency
106 * struct timing_regs - AXI I2C timing registers that depend on I2C spec
121 /* Reg values in ns derived from I2C spec and AXI I2C PG for different frequencies */
148 * setting i2c clock frequency for the line.
235 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) argument
236 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) argument
238 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num);
239 static void __xiic_start_xfer(struct xiic_i2c *i2c);
249 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) in xiic_setreg8() argument
251 if (i2c->endianness == LITTLE) in xiic_setreg8()
252 iowrite8(value, i2c->base + reg); in xiic_setreg8()
254 iowrite8(value, i2c->base + reg + 3); in xiic_setreg8()
257 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) in xiic_getreg8() argument
261 if (i2c->endianness == LITTLE) in xiic_getreg8()
262 ret = ioread8(i2c->base + reg); in xiic_getreg8()
264 ret = ioread8(i2c->base + reg + 3); in xiic_getreg8()
268 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) in xiic_setreg16() argument
270 if (i2c->endianness == LITTLE) in xiic_setreg16()
271 iowrite16(value, i2c->base + reg); in xiic_setreg16()
273 iowrite16be(value, i2c->base + reg + 2); in xiic_setreg16()
276 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) in xiic_setreg32() argument
278 if (i2c->endianness == LITTLE) in xiic_setreg32()
279 iowrite32(value, i2c->base + reg); in xiic_setreg32()
281 iowrite32be(value, i2c->base + reg); in xiic_setreg32()
284 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) in xiic_getreg32() argument
288 if (i2c->endianness == LITTLE) in xiic_getreg32()
289 ret = ioread32(i2c->base + reg); in xiic_getreg32()
291 ret = ioread32be(i2c->base + reg); in xiic_getreg32()
295 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) in xiic_irq_dis() argument
297 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_irq_dis()
299 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); in xiic_irq_dis()
302 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) in xiic_irq_en() argument
304 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_irq_en()
306 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); in xiic_irq_en()
309 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) in xiic_irq_clr() argument
311 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_irq_clr()
313 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); in xiic_irq_clr()
316 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) in xiic_irq_clr_en() argument
318 xiic_irq_clr(i2c, mask); in xiic_irq_clr_en()
319 xiic_irq_en(i2c, mask); in xiic_irq_clr_en()
322 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) in xiic_clear_rx_fifo() argument
328 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); in xiic_clear_rx_fifo()
330 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { in xiic_clear_rx_fifo()
331 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); in xiic_clear_rx_fifo()
333 dev_err(i2c->dev, "Failed to clear rx fifo\n"); in xiic_clear_rx_fifo()
341 static int xiic_wait_tx_empty(struct xiic_i2c *i2c) in xiic_wait_tx_empty() argument
347 for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_wait_tx_empty()
349 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) { in xiic_wait_tx_empty()
351 dev_err(i2c->dev, "Timeout waiting at Tx empty\n"); in xiic_wait_tx_empty()
361 * @i2c: Pointer to the xiic device structure
365 * AXI I2C PG and NXP I2C Spec.
371 static int xiic_setclk(struct xiic_i2c *i2c) in xiic_setclk() argument
377 dev_dbg(i2c->adap.dev.parent, in xiic_setclk()
378 "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n", in xiic_setclk()
379 __func__, i2c->input_clk, i2c->i2c_clk); in xiic_setclk()
382 if (!i2c->i2c_clk || !i2c->input_clk) in xiic_setclk()
385 clk_in_mhz = DIV_ROUND_UP(i2c->input_clk, 1000000); in xiic_setclk()
387 switch (i2c->i2c_clk) { in xiic_setclk()
398 dev_warn(i2c->adap.dev.parent, "Unsupported scl frequency\n"); in xiic_setclk()
405 * period to get the number of clock cycles required. Refer Xilinx AXI I2C in xiic_setclk()
406 * PG document and I2C specification for further details. in xiic_setclk()
410 reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7; in xiic_setclk()
414 xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1); in xiic_setclk()
417 xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1); in xiic_setclk()
421 xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1); in xiic_setclk()
425 xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1); in xiic_setclk()
429 xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1); in xiic_setclk()
433 xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1); in xiic_setclk()
437 xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1); in xiic_setclk()
440 xiic_setreg32(i2c, XIIC_THDDAT_REG_OFFSET, 1); in xiic_setclk()
445 static int xiic_reinit(struct xiic_i2c *i2c) in xiic_reinit() argument
449 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); in xiic_reinit()
451 ret = xiic_setclk(i2c); in xiic_reinit()
456 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); in xiic_reinit()
459 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); in xiic_reinit()
462 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); in xiic_reinit()
465 ret = xiic_clear_rx_fifo(i2c); in xiic_reinit()
470 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); in xiic_reinit()
472 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); in xiic_reinit()
477 static void xiic_deinit(struct xiic_i2c *i2c) in xiic_deinit() argument
481 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); in xiic_deinit()
484 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_deinit()
485 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); in xiic_deinit()
488 static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c) in xiic_smbus_block_read_setup() argument
496 i2c->rx_msg->flags &= ~I2C_M_RECV_LEN; in xiic_smbus_block_read_setup()
499 i2c->smbus_block_read = true; in xiic_smbus_block_read_setup()
502 rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); in xiic_smbus_block_read_setup()
504 i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len; in xiic_smbus_block_read_setup()
515 i2c->rx_msg->len = rxmsg_len + 1; in xiic_smbus_block_read_setup()
524 i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN; in xiic_smbus_block_read_setup()
531 i2c->rx_msg->len = rxmsg_len + 1; in xiic_smbus_block_read_setup()
533 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); in xiic_smbus_block_read_setup()
539 i2c->tx_msg->len = 3; in xiic_smbus_block_read_setup()
540 i2c->smbus_block_read = false; in xiic_smbus_block_read_setup()
541 dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n"); in xiic_smbus_block_read_setup()
544 static void xiic_read_rx(struct xiic_i2c *i2c) in xiic_read_rx() argument
550 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; in xiic_read_rx()
552 dev_dbg(i2c->adap.dev.parent, in xiic_read_rx()
554 __func__, bytes_in_fifo, xiic_rx_space(i2c), in xiic_read_rx()
555 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), in xiic_read_rx()
556 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_read_rx()
558 if (bytes_in_fifo > xiic_rx_space(i2c)) in xiic_read_rx()
559 bytes_in_fifo = xiic_rx_space(i2c); in xiic_read_rx()
563 if (!i2c->dynamic) { in xiic_read_rx()
564 bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo; in xiic_read_rx()
567 if (i2c->rx_msg->flags & I2C_M_RECV_LEN) { in xiic_read_rx()
568 xiic_smbus_block_read_setup(i2c); in xiic_read_rx()
579 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_read_rx()
580 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | in xiic_read_rx()
586 if (i2c->nmsgs == 1) { in xiic_read_rx()
587 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_read_rx()
588 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & in xiic_read_rx()
593 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_read_rx()
594 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & in xiic_read_rx()
601 i2c->rx_msg->buf[i2c->rx_pos++] = in xiic_read_rx()
602 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); in xiic_read_rx()
605 if (i2c->dynamic) { in xiic_read_rx()
609 bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH); in xiic_read_rx()
611 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); in xiic_read_rx()
615 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) in xiic_tx_fifo_space() argument
618 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; in xiic_tx_fifo_space()
621 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) in xiic_fill_tx_fifo() argument
623 u8 fifo_space = xiic_tx_fifo_space(i2c); in xiic_fill_tx_fifo()
624 int len = xiic_tx_space(i2c); in xiic_fill_tx_fifo()
628 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", in xiic_fill_tx_fifo()
632 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; in xiic_fill_tx_fifo()
634 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { in xiic_fill_tx_fifo()
636 if (i2c->dynamic) { in xiic_fill_tx_fifo()
643 status = xiic_wait_tx_empty(i2c); in xiic_fill_tx_fifo()
648 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_fill_tx_fifo()
649 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & in xiic_fill_tx_fifo()
652 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); in xiic_fill_tx_fifo()
654 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); in xiic_fill_tx_fifo()
658 static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code) in xiic_wakeup() argument
660 i2c->tx_msg = NULL; in xiic_wakeup()
661 i2c->rx_msg = NULL; in xiic_wakeup()
662 i2c->nmsgs = 0; in xiic_wakeup()
663 i2c->state = code; in xiic_wakeup()
664 complete(&i2c->completion); in xiic_wakeup()
669 struct xiic_i2c *i2c = dev_id; in xiic_process() local
682 mutex_lock(&i2c->lock); in xiic_process()
683 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_process()
684 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_process()
687 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", in xiic_process()
689 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", in xiic_process()
690 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), in xiic_process()
691 i2c->tx_msg, i2c->nmsgs); in xiic_process()
692 dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n", in xiic_process()
693 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), in xiic_process()
694 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_process()
706 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); in xiic_process()
712 ret = xiic_reinit(i2c); in xiic_process()
714 dev_dbg(i2c->adap.dev.parent, "reinit failed\n"); in xiic_process()
716 if (i2c->rx_msg) { in xiic_process()
720 if (i2c->tx_msg) { in xiic_process()
731 if (!i2c->rx_msg) { in xiic_process()
732 dev_dbg(i2c->adap.dev.parent, in xiic_process()
734 xiic_clear_rx_fifo(i2c); in xiic_process()
738 xiic_read_rx(i2c); in xiic_process()
739 if (xiic_rx_space(i2c) == 0) { in xiic_process()
741 i2c->rx_msg = NULL; in xiic_process()
746 dev_dbg(i2c->adap.dev.parent, in xiic_process()
748 __func__, i2c->nmsgs); in xiic_process()
754 if (i2c->nmsgs > 1) { in xiic_process()
755 i2c->nmsgs--; in xiic_process()
756 i2c->tx_msg++; in xiic_process()
757 dev_dbg(i2c->adap.dev.parent, in xiic_process()
769 if (!i2c->tx_msg) { in xiic_process()
770 dev_dbg(i2c->adap.dev.parent, in xiic_process()
775 if (xiic_tx_space(i2c)) { in xiic_process()
776 xiic_fill_tx_fifo(i2c); in xiic_process()
779 dev_dbg(i2c->adap.dev.parent, in xiic_process()
781 __func__, i2c->nmsgs); in xiic_process()
785 if (i2c->nmsgs > 1 && (pend & XIIC_INTR_TX_EMPTY_MASK)) { in xiic_process()
786 i2c->nmsgs--; in xiic_process()
787 i2c->tx_msg++; in xiic_process()
790 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); in xiic_process()
792 dev_dbg(i2c->adap.dev.parent, in xiic_process()
804 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); in xiic_process()
806 if (i2c->tx_msg && i2c->smbus_block_read) { in xiic_process()
807 i2c->smbus_block_read = false; in xiic_process()
809 i2c->tx_msg->len = 1; in xiic_process()
812 if (!i2c->tx_msg) in xiic_process()
817 if (i2c->nmsgs == 1 && !i2c->rx_msg && in xiic_process()
818 xiic_tx_space(i2c) == 0) in xiic_process()
825 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); in xiic_process()
827 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); in xiic_process()
829 __xiic_start_xfer(i2c); in xiic_process()
831 xiic_wakeup(i2c, wakeup_code); in xiic_process()
835 mutex_unlock(&i2c->lock); in xiic_process()
839 static int xiic_bus_busy(struct xiic_i2c *i2c) in xiic_bus_busy() argument
841 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); in xiic_bus_busy()
846 static int xiic_wait_not_busy(struct xiic_i2c *i2c) in xiic_wait_not_busy() argument
855 err = xiic_bus_busy(i2c); in xiic_wait_not_busy()
858 err = xiic_bus_busy(i2c); in xiic_wait_not_busy()
864 static void xiic_start_recv(struct xiic_i2c *i2c) in xiic_start_recv() argument
868 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; in xiic_start_recv()
870 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", in xiic_start_recv()
871 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), in xiic_start_recv()
872 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_start_recv()
875 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK); in xiic_start_recv()
877 if (i2c->dynamic) { in xiic_start_recv()
882 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | in xiic_start_recv()
898 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); in xiic_start_recv()
901 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, in xiic_start_recv()
906 val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0; in xiic_start_recv()
909 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); in xiic_start_recv()
911 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); in xiic_start_recv()
919 if (i2c->prev_msg_tx) { in xiic_start_recv()
922 status = xiic_wait_tx_empty(i2c); in xiic_start_recv()
927 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_start_recv()
937 if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) { in xiic_start_recv()
949 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | in xiic_start_recv()
954 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); in xiic_start_recv()
957 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | in xiic_start_recv()
961 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, in xiic_start_recv()
966 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | in xiic_start_recv()
970 dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n", in xiic_start_recv()
971 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), in xiic_start_recv()
972 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_start_recv()
975 if (i2c->nmsgs == 1) in xiic_start_recv()
977 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); in xiic_start_recv()
980 i2c->tx_pos = msg->len; in xiic_start_recv()
983 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); in xiic_start_recv()
985 i2c->prev_msg_tx = false; in xiic_start_recv()
988 static void xiic_start_send(struct xiic_i2c *i2c) in xiic_start_send() argument
992 struct i2c_msg *msg = i2c->tx_msg; in xiic_start_send()
994 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", in xiic_start_send()
996 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", in xiic_start_send()
997 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), in xiic_start_send()
998 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_start_send()
1000 if (i2c->dynamic) { in xiic_start_send()
1005 if (i2c->nmsgs == 1 && msg->len == 0) in xiic_start_send()
1009 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); in xiic_start_send()
1012 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | in xiic_start_send()
1015 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? in xiic_start_send()
1018 xiic_fill_tx_fifo(i2c); in xiic_start_send()
1026 if (i2c->prev_msg_tx) { in xiic_start_send()
1029 status = xiic_wait_tx_empty(i2c); in xiic_start_send()
1034 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_start_send()
1037 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | in xiic_start_send()
1045 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); in xiic_start_send()
1048 xiic_fill_tx_fifo(i2c); in xiic_start_send()
1052 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_start_send()
1053 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | in xiic_start_send()
1059 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | in xiic_start_send()
1063 i2c->prev_msg_tx = true; in xiic_start_send()
1066 static void __xiic_start_xfer(struct xiic_i2c *i2c) in __xiic_start_xfer() argument
1068 int fifo_space = xiic_tx_fifo_space(i2c); in __xiic_start_xfer()
1070 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", in __xiic_start_xfer()
1071 __func__, i2c->tx_msg, fifo_space); in __xiic_start_xfer()
1073 if (!i2c->tx_msg) in __xiic_start_xfer()
1076 i2c->rx_pos = 0; in __xiic_start_xfer()
1077 i2c->tx_pos = 0; in __xiic_start_xfer()
1078 i2c->state = STATE_START; in __xiic_start_xfer()
1079 if (i2c->tx_msg->flags & I2C_M_RD) { in __xiic_start_xfer()
1081 xiic_start_recv(i2c); in __xiic_start_xfer()
1083 xiic_start_send(i2c); in __xiic_start_xfer()
1087 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) in xiic_start_xfer() argument
1092 mutex_lock(&i2c->lock); in xiic_start_xfer()
1094 if (i2c->tx_msg || i2c->rx_msg) { in xiic_start_xfer()
1095 dev_err(i2c->adap.dev.parent, in xiic_start_xfer()
1103 * should ignore it, since bus will never be released and i2c will be in xiic_start_xfer()
1106 if (!i2c->singlemaster) { in xiic_start_xfer()
1107 ret = xiic_wait_not_busy(i2c); in xiic_start_xfer()
1114 dev_warn(i2c->adap.dev.parent, "I2C bus busy timeout, reinitializing\n"); in xiic_start_xfer()
1115 ret = xiic_reinit(i2c); in xiic_start_xfer()
1118 ret = xiic_wait_not_busy(i2c); in xiic_start_xfer()
1124 i2c->tx_msg = msgs; in xiic_start_xfer()
1125 i2c->rx_msg = NULL; in xiic_start_xfer()
1126 i2c->nmsgs = num; in xiic_start_xfer()
1127 init_completion(&i2c->completion); in xiic_start_xfer()
1130 i2c->dynamic = true; in xiic_start_xfer()
1133 i2c->prev_msg_tx = false; in xiic_start_xfer()
1144 for (count = 0; count < i2c->nmsgs; count++) { in xiic_start_xfer()
1145 broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) && in xiic_start_xfer()
1146 (i2c->tx_msg[count].flags & I2C_M_RD); in xiic_start_xfer()
1147 max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) && in xiic_start_xfer()
1148 (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC); in xiic_start_xfer()
1149 smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN); in xiic_start_xfer()
1152 i2c->dynamic = false; in xiic_start_xfer()
1157 ret = xiic_reinit(i2c); in xiic_start_xfer()
1159 __xiic_start_xfer(i2c); in xiic_start_xfer()
1162 mutex_unlock(&i2c->lock); in xiic_start_xfer()
1169 struct xiic_i2c *i2c = i2c_get_adapdata(adap); in xiic_xfer() local
1173 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); in xiic_xfer()
1175 err = pm_runtime_resume_and_get(i2c->dev); in xiic_xfer()
1179 err = xiic_start_xfer(i2c, msgs, num); in xiic_xfer()
1183 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT); in xiic_xfer()
1184 mutex_lock(&i2c->lock); in xiic_xfer()
1186 i2c->tx_msg = NULL; in xiic_xfer()
1187 i2c->rx_msg = NULL; in xiic_xfer()
1188 i2c->nmsgs = 0; in xiic_xfer()
1191 err = (i2c->state == STATE_DONE) ? num : -EIO; in xiic_xfer()
1193 mutex_unlock(&i2c->lock); in xiic_xfer()
1196 pm_runtime_mark_last_busy(i2c->dev); in xiic_xfer()
1197 pm_runtime_put_autosuspend(i2c->dev); in xiic_xfer()
1232 struct xiic_i2c *i2c; in xiic_i2c_probe() local
1240 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); in xiic_i2c_probe()
1241 if (!i2c) in xiic_i2c_probe()
1248 i2c->quirks = data->quirks; in xiic_i2c_probe()
1251 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in xiic_i2c_probe()
1252 if (IS_ERR(i2c->base)) in xiic_i2c_probe()
1253 return PTR_ERR(i2c->base); in xiic_i2c_probe()
1262 platform_set_drvdata(pdev, i2c); in xiic_i2c_probe()
1263 i2c->adap = xiic_adapter; in xiic_i2c_probe()
1264 i2c_set_adapdata(&i2c->adap, i2c); in xiic_i2c_probe()
1265 i2c->adap.dev.parent = &pdev->dev; in xiic_i2c_probe()
1266 i2c->adap.dev.of_node = pdev->dev.of_node; in xiic_i2c_probe()
1267 snprintf(i2c->adap.name, sizeof(i2c->adap.name), in xiic_i2c_probe()
1270 mutex_init(&i2c->lock); in xiic_i2c_probe()
1272 i2c->clk = devm_clk_get_enabled(&pdev->dev, NULL); in xiic_i2c_probe()
1273 if (IS_ERR(i2c->clk)) in xiic_i2c_probe()
1274 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), in xiic_i2c_probe()
1277 i2c->dev = &pdev->dev; in xiic_i2c_probe()
1278 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); in xiic_i2c_probe()
1279 pm_runtime_use_autosuspend(i2c->dev); in xiic_i2c_probe()
1280 pm_runtime_set_active(i2c->dev); in xiic_i2c_probe()
1281 pm_runtime_enable(i2c->dev); in xiic_i2c_probe()
1284 i2c->input_clk = clk_get_rate(i2c->clk); in xiic_i2c_probe()
1286 &i2c->i2c_clk); in xiic_i2c_probe()
1288 if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ) in xiic_i2c_probe()
1289 i2c->i2c_clk = 0; in xiic_i2c_probe()
1293 pdev->name, i2c); in xiic_i2c_probe()
1300 i2c->singlemaster = in xiic_i2c_probe()
1308 i2c->endianness = LITTLE; in xiic_i2c_probe()
1309 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); in xiic_i2c_probe()
1311 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); in xiic_i2c_probe()
1313 i2c->endianness = BIG; in xiic_i2c_probe()
1315 ret = xiic_reinit(i2c); in xiic_i2c_probe()
1321 /* add i2c adapter to i2c tree */ in xiic_i2c_probe()
1322 ret = i2c_add_adapter(&i2c->adap); in xiic_i2c_probe()
1324 xiic_deinit(i2c); in xiic_i2c_probe()
1331 i2c_new_client_device(&i2c->adap, pdata->devices + i); in xiic_i2c_probe()
1335 (unsigned long)res->start, irq, i2c->i2c_clk); in xiic_i2c_probe()
1348 struct xiic_i2c *i2c = platform_get_drvdata(pdev); in xiic_i2c_remove() local
1352 i2c_del_adapter(&i2c->adap); in xiic_i2c_remove()
1354 ret = pm_runtime_get_sync(i2c->dev); in xiic_i2c_remove()
1360 xiic_deinit(i2c); in xiic_i2c_remove()
1362 pm_runtime_put_sync(i2c->dev); in xiic_i2c_remove()
1370 struct xiic_i2c *i2c = dev_get_drvdata(dev); in xiic_i2c_runtime_suspend() local
1372 clk_disable(i2c->clk); in xiic_i2c_runtime_suspend()
1379 struct xiic_i2c *i2c = dev_get_drvdata(dev); in xiic_i2c_runtime_resume() local
1382 ret = clk_enable(i2c->clk); in xiic_i2c_runtime_resume()
1410 MODULE_DESCRIPTION("Xilinx I2C bus driver");