Lines Matching +full:i2c +full:- +full:fast +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/i2c/busses/i2c-tegra.c
14 #include <linux/dma-mapping.h>
16 #include <linux/i2c.h>
51 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
52 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
130 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
131 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
144 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
154 * @MSG_END_REPEAT_START: Send repeat-start.
155 * @MSG_END_CONTINUE: Don't send stop or repeat-start.
165 * @has_continue_xfer_support: continue-transfer supported
170 * @clk_divisor_hs_mode: Clock divisor in HS mode.
171 * @clk_divisor_std_mode: Clock divisor in standard mode. It is
172 * applicable if there is no fast clock source i.e. single clock
174 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
175 * applicable if there is no fast clock source i.e. single clock
177 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
178 * applicable if there is no fast clock source (i.e. single
180 * @has_multi_master_mode: The I2C controller supports running in single-master
181 * or multi-master mode.
182 * @has_slcg_override_reg: The I2C controller supports a register that
184 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
187 * @quirks: I2C adapter quirks for limiting write/read transfer size and not
192 * @tlow_std_mode: Low period of the clock in standard mode.
193 * @thigh_std_mode: High period of the clock in standard mode.
194 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
195 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
197 * in standard mode.
199 * conditions in fast/fast-plus modes.
201 * in HS mode.
230 * struct tegra_i2c_dev - per device I2C context
232 * @hw: Tegra I2C HW feature
233 * @adapter: core I2C layer adapter information
234 * @div_clk: clock reference for div clock of I2C controller
235 * @clocks: array of I2C controller clocks
237 * @rst: reset control for the I2C controller
239 * @base_phys: physical base address of the I2C controller
240 * @cont_id: I2C controller ID, used for packet header
242 * @is_dvc: identifies the DVC I2C controller, has a different register layout
243 * @is_vi: identifies the VI I2C controller, has a different register layout
250 * @timings: i2c timings information like bus frequency
251 * @multimaster_mode: indicates that I2C controller is in multi-master mode
299 #define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && (dev)->is_dvc)
300 #define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && (dev)->is_vi)
305 writel_relaxed(val, i2c_dev->base + reg); in dvc_writel()
310 return readl_relaxed(i2c_dev->base + reg); in dvc_readl()
315 * in order to talk to the I2C block inside the DVC block.
329 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_writel()
333 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_writel()
335 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS)); in i2c_writel()
340 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_readl()
346 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); in i2c_writesl()
355 * VI I2C controller has known hardware bug where writes get stuck in i2c_writesl_vi()
357 * Recommended software work around is to read I2C register after in i2c_writesl_vi()
360 while (len--) in i2c_writesl_vi()
367 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); in i2c_readsl()
390 complete(&i2c_dev->dma_complete); in tegra_i2c_dma_complete()
398 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); in tegra_i2c_dma_submit()
400 reinit_completion(&i2c_dev->dma_complete); in tegra_i2c_dma_submit()
402 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; in tegra_i2c_dma_submit()
404 dma_desc = dmaengine_prep_slave_single(i2c_dev->dma_chan, i2c_dev->dma_phys, in tegra_i2c_dma_submit()
408 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n", in tegra_i2c_dma_submit()
409 i2c_dev->msg_read ? "RX" : "TX"); in tegra_i2c_dma_submit()
410 return -EINVAL; in tegra_i2c_dma_submit()
413 dma_desc->callback = tegra_i2c_dma_complete; in tegra_i2c_dma_submit()
414 dma_desc->callback_param = i2c_dev; in tegra_i2c_dma_submit()
417 dma_async_issue_pending(i2c_dev->dma_chan); in tegra_i2c_dma_submit()
424 if (i2c_dev->dma_buf) { in tegra_i2c_release_dma()
425 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, in tegra_i2c_release_dma()
426 i2c_dev->dma_buf, i2c_dev->dma_phys); in tegra_i2c_release_dma()
427 i2c_dev->dma_buf = NULL; in tegra_i2c_release_dma()
430 if (i2c_dev->dma_chan) { in tegra_i2c_release_dma()
431 dma_release_channel(i2c_dev->dma_chan); in tegra_i2c_release_dma()
432 i2c_dev->dma_chan = NULL; in tegra_i2c_release_dma()
445 if (i2c_dev->hw->has_apb_dma) { in tegra_i2c_init_dma()
447 dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n"); in tegra_i2c_init_dma()
451 dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n"); in tegra_i2c_init_dma()
460 i2c_dev->dma_chan = dma_request_chan(i2c_dev->dev, "tx"); in tegra_i2c_init_dma()
461 if (IS_ERR(i2c_dev->dma_chan)) { in tegra_i2c_init_dma()
462 err = PTR_ERR(i2c_dev->dma_chan); in tegra_i2c_init_dma()
463 i2c_dev->dma_chan = NULL; in tegra_i2c_init_dma()
467 i2c_dev->dma_dev = i2c_dev->dma_chan->device->dev; in tegra_i2c_init_dma()
468 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len + in tegra_i2c_init_dma()
471 dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, in tegra_i2c_init_dma()
474 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n"); in tegra_i2c_init_dma()
475 err = -ENOMEM; in tegra_i2c_init_dma()
479 i2c_dev->dma_buf = dma_buf; in tegra_i2c_init_dma()
480 i2c_dev->dma_phys = dma_phys; in tegra_i2c_init_dma()
486 if (err != -EPROBE_DEFER) { in tegra_i2c_init_dma()
487 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); in tegra_i2c_init_dma()
488 dev_err(i2c_dev->dev, "falling back to PIO\n"); in tegra_i2c_init_dma()
496 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
497 * block. This block is identical to the rest of the I2C blocks, except that
498 * it only supports master mode, it has registers moved around, and it needs
499 * some extra init to get it into I2C mode. The register moves are handled
549 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); in tegra_i2c_poll_register()
552 if (!i2c_dev->atomic_mode) in tegra_i2c_poll_register()
565 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_flush_fifos()
581 dev_err(i2c_dev->dev, "failed to flush FIFO\n"); in tegra_i2c_flush_fifos()
592 if (!i2c_dev->hw->has_config_load_reg) in tegra_i2c_wait_for_config_load()
600 dev_err(i2c_dev->dev, "failed to load config\n"); in tegra_i2c_wait_for_config_load()
610 acpi_handle handle = ACPI_HANDLE(i2c_dev->dev); in tegra_i2c_init()
611 struct i2c_timings *t = &i2c_dev->timings; in tegra_i2c_init()
618 * kernel boot up since voltage regulators use I2C. Hence, we will in tegra_i2c_init()
625 err = reset_control_reset(i2c_dev->rst); in tegra_i2c_init()
635 if (i2c_dev->hw->has_multi_master_mode) in tegra_i2c_init()
644 switch (t->bus_freq_hz) { in tegra_i2c_init()
647 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; in tegra_i2c_init()
648 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; in tegra_i2c_init()
649 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; in tegra_i2c_init()
651 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) in tegra_i2c_init()
652 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; in tegra_i2c_init()
654 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; in tegra_i2c_init()
658 tlow = i2c_dev->hw->tlow_std_mode; in tegra_i2c_init()
659 thigh = i2c_dev->hw->thigh_std_mode; in tegra_i2c_init()
660 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; in tegra_i2c_init()
661 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; in tegra_i2c_init()
667 i2c_dev->hw->clk_divisor_hs_mode) | in tegra_i2c_init()
671 if (i2c_dev->hw->has_interface_timing_reg) { in tegra_i2c_init()
678 * Configure setup and hold times only when tsu_thd is non-zero. in tegra_i2c_init()
681 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) in tegra_i2c_init()
686 err = clk_set_rate(i2c_dev->div_clk, in tegra_i2c_init()
687 t->bus_freq_hz * clk_multiplier); in tegra_i2c_init()
689 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); in tegra_i2c_init()
706 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) in tegra_i2c_init()
721 * NACK interrupt is generated before the I2C controller generates in tegra_i2c_disable_packet_mode()
726 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz)); in tegra_i2c_disable_packet_mode()
737 size_t buf_remaining = i2c_dev->msg_buf_remaining; in tegra_i2c_empty_rx_fifo()
739 u8 *buf = i2c_dev->msg_buf; in tegra_i2c_empty_rx_fifo()
746 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) in tegra_i2c_empty_rx_fifo()
747 return -EINVAL; in tegra_i2c_empty_rx_fifo()
749 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_empty_rx_fifo()
765 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_empty_rx_fifo()
766 rx_fifo_avail -= words_to_transfer; in tegra_i2c_empty_rx_fifo()
782 rx_fifo_avail--; in tegra_i2c_empty_rx_fifo()
787 return -EINVAL; in tegra_i2c_empty_rx_fifo()
789 i2c_dev->msg_buf_remaining = buf_remaining; in tegra_i2c_empty_rx_fifo()
790 i2c_dev->msg_buf = buf; in tegra_i2c_empty_rx_fifo()
797 size_t buf_remaining = i2c_dev->msg_buf_remaining; in tegra_i2c_fill_tx_fifo()
799 u8 *buf = i2c_dev->msg_buf; in tegra_i2c_fill_tx_fifo()
802 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_fill_tx_fifo()
830 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_fill_tx_fifo()
831 tx_fifo_avail -= words_to_transfer; in tegra_i2c_fill_tx_fifo()
833 i2c_dev->msg_buf_remaining = buf_remaining; in tegra_i2c_fill_tx_fifo()
834 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_fill_tx_fifo()
853 * in this function for non-zero words_to_transfer. in tegra_i2c_fill_tx_fifo()
858 i2c_dev->msg_buf_remaining = 0; in tegra_i2c_fill_tx_fifo()
859 i2c_dev->msg_buf = NULL; in tegra_i2c_fill_tx_fifo()
876 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", in tegra_i2c_isr()
880 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; in tegra_i2c_isr()
887 i2c_dev->msg_err |= I2C_ERR_NO_ACK; in tegra_i2c_isr()
889 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; in tegra_i2c_isr()
894 * I2C transfer is terminated during the bus clear, so skip in tegra_i2c_isr()
897 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) in tegra_i2c_isr()
900 if (!i2c_dev->dma_mode) { in tegra_i2c_isr()
901 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { in tegra_i2c_isr()
908 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; in tegra_i2c_isr()
913 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { in tegra_i2c_isr()
914 if (i2c_dev->msg_buf_remaining) in tegra_i2c_isr()
932 * so forcing msg_buf_remaining to 0 in DMA mode. in tegra_i2c_isr()
935 if (i2c_dev->dma_mode) in tegra_i2c_isr()
936 i2c_dev->msg_buf_remaining = 0; in tegra_i2c_isr()
941 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { in tegra_i2c_isr()
942 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; in tegra_i2c_isr()
945 complete(&i2c_dev->msg_complete); in tegra_i2c_isr()
957 if (i2c_dev->hw->supports_bus_clear) in tegra_i2c_isr()
965 if (i2c_dev->dma_mode) { in tegra_i2c_isr()
966 dmaengine_terminate_async(i2c_dev->dma_chan); in tegra_i2c_isr()
967 complete(&i2c_dev->dma_complete); in tegra_i2c_isr()
970 complete(&i2c_dev->msg_complete); in tegra_i2c_isr()
982 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
987 if (i2c_dev->dma_mode) { in tegra_i2c_config_fifo_trig()
995 if (i2c_dev->msg_read) { in tegra_i2c_config_fifo_trig()
998 slv_config.src_addr = i2c_dev->base_phys + reg_offset; in tegra_i2c_config_fifo_trig()
1002 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
1009 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; in tegra_i2c_config_fifo_trig()
1013 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
1020 err = dmaengine_slave_config(i2c_dev->dma_chan, &slv_config); in tegra_i2c_config_fifo_trig()
1022 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err); in tegra_i2c_config_fifo_trig()
1023 dev_err(i2c_dev->dev, "falling back to PIO\n"); in tegra_i2c_config_fifo_trig()
1026 i2c_dev->dma_mode = false; in tegra_i2c_config_fifo_trig()
1032 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
1053 tegra_i2c_isr(i2c_dev->irq, i2c_dev); in tegra_i2c_poll_completion()
1074 if (i2c_dev->atomic_mode) { in tegra_i2c_wait_completion()
1077 enable_irq(i2c_dev->irq); in tegra_i2c_wait_completion()
1080 disable_irq(i2c_dev->irq); in tegra_i2c_wait_completion()
1086 * case we will get timeout if I2C transfer is running on in tegra_i2c_wait_completion()
1105 reinit_completion(&i2c_dev->msg_complete); in tegra_i2c_issue_bus_clear()
1119 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50); in tegra_i2c_issue_bus_clear()
1123 dev_err(i2c_dev->dev, "failed to clear bus\n"); in tegra_i2c_issue_bus_clear()
1124 return -ETIMEDOUT; in tegra_i2c_issue_bus_clear()
1129 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); in tegra_i2c_issue_bus_clear()
1130 return -EIO; in tegra_i2c_issue_bus_clear()
1133 return -EAGAIN; in tegra_i2c_issue_bus_clear()
1140 u32 *dma_buf = i2c_dev->dma_buf; in tegra_i2c_push_packet_header()
1146 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) | in tegra_i2c_push_packet_header()
1149 if (i2c_dev->dma_mode && !i2c_dev->msg_read) in tegra_i2c_push_packet_header()
1154 packet_header = i2c_dev->msg_len - 1; in tegra_i2c_push_packet_header()
1156 if (i2c_dev->dma_mode && !i2c_dev->msg_read) in tegra_i2c_push_packet_header()
1168 if (msg->flags & I2C_M_TEN) { in tegra_i2c_push_packet_header()
1169 packet_header |= msg->addr; in tegra_i2c_push_packet_header()
1172 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; in tegra_i2c_push_packet_header()
1175 if (msg->flags & I2C_M_IGNORE_NAK) in tegra_i2c_push_packet_header()
1178 if (msg->flags & I2C_M_RD) in tegra_i2c_push_packet_header()
1181 if (i2c_dev->dma_mode && !i2c_dev->msg_read) in tegra_i2c_push_packet_header()
1190 if (i2c_dev->msg_err == I2C_ERR_NONE) in tegra_i2c_error_recover()
1195 /* start recovery upon arbitration loss in single master mode */ in tegra_i2c_error_recover()
1196 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { in tegra_i2c_error_recover()
1197 if (!i2c_dev->multimaster_mode) in tegra_i2c_error_recover()
1198 return i2c_recover_bus(&i2c_dev->adapter); in tegra_i2c_error_recover()
1200 return -EAGAIN; in tegra_i2c_error_recover()
1203 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { in tegra_i2c_error_recover()
1204 if (msg->flags & I2C_M_IGNORE_NAK) in tegra_i2c_error_recover()
1207 return -EREMOTEIO; in tegra_i2c_error_recover()
1210 return -EIO; in tegra_i2c_error_recover()
1226 i2c_dev->msg_buf = msg->buf; in tegra_i2c_xfer_msg()
1227 i2c_dev->msg_len = msg->len; in tegra_i2c_xfer_msg()
1229 i2c_dev->msg_err = I2C_ERR_NONE; in tegra_i2c_xfer_msg()
1230 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD); in tegra_i2c_xfer_msg()
1231 reinit_completion(&i2c_dev->msg_complete); in tegra_i2c_xfer_msg()
1238 if (msg->flags & I2C_M_RECV_LEN) { in tegra_i2c_xfer_msg()
1240 i2c_dev->msg_len = 1; in tegra_i2c_xfer_msg()
1242 i2c_dev->msg_buf += 1; in tegra_i2c_xfer_msg()
1243 i2c_dev->msg_len -= 1; in tegra_i2c_xfer_msg()
1247 i2c_dev->msg_buf_remaining = i2c_dev->msg_len; in tegra_i2c_xfer_msg()
1249 if (i2c_dev->msg_read) in tegra_i2c_xfer_msg()
1250 xfer_size = i2c_dev->msg_len; in tegra_i2c_xfer_msg()
1252 xfer_size = i2c_dev->msg_len + I2C_PACKET_HEADER_SIZE; in tegra_i2c_xfer_msg()
1256 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN && in tegra_i2c_xfer_msg()
1257 i2c_dev->dma_buf && !i2c_dev->atomic_mode; in tegra_i2c_xfer_msg()
1266 i2c_dev->timings.bus_freq_hz); in tegra_i2c_xfer_msg()
1271 if (i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1272 if (i2c_dev->msg_read) { in tegra_i2c_xfer_msg()
1273 dma_sync_single_for_device(i2c_dev->dma_dev, in tegra_i2c_xfer_msg()
1274 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1281 dma_sync_single_for_cpu(i2c_dev->dma_dev, in tegra_i2c_xfer_msg()
1282 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1289 if (!i2c_dev->msg_read) { in tegra_i2c_xfer_msg()
1290 if (i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1291 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, in tegra_i2c_xfer_msg()
1292 msg->buf, i2c_dev->msg_len); in tegra_i2c_xfer_msg()
1294 dma_sync_single_for_device(i2c_dev->dma_dev, in tegra_i2c_xfer_msg()
1295 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1306 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) in tegra_i2c_xfer_msg()
1309 if (!i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1310 if (msg->flags & I2C_M_RD) in tegra_i2c_xfer_msg()
1312 else if (i2c_dev->msg_buf_remaining) in tegra_i2c_xfer_msg()
1317 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", in tegra_i2c_xfer_msg()
1320 if (i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1322 &i2c_dev->dma_complete, in tegra_i2c_xfer_msg()
1330 dmaengine_synchronize(i2c_dev->dma_chan); in tegra_i2c_xfer_msg()
1331 dmaengine_terminate_sync(i2c_dev->dma_chan); in tegra_i2c_xfer_msg()
1333 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { in tegra_i2c_xfer_msg()
1335 return -ETIMEDOUT; in tegra_i2c_xfer_msg()
1338 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { in tegra_i2c_xfer_msg()
1339 dma_sync_single_for_cpu(i2c_dev->dma_dev, in tegra_i2c_xfer_msg()
1340 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1343 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len); in tegra_i2c_xfer_msg()
1347 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, in tegra_i2c_xfer_msg()
1354 return -ETIMEDOUT; in tegra_i2c_xfer_msg()
1357 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", in tegra_i2c_xfer_msg()
1358 time_left, completion_done(&i2c_dev->msg_complete), in tegra_i2c_xfer_msg()
1359 i2c_dev->msg_err); in tegra_i2c_xfer_msg()
1361 i2c_dev->dma_mode = false; in tegra_i2c_xfer_msg()
1376 ret = pm_runtime_get_sync(i2c_dev->dev); in tegra_i2c_xfer()
1378 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); in tegra_i2c_xfer()
1379 pm_runtime_put_noidle(i2c_dev->dev); in tegra_i2c_xfer()
1386 if (i < (num - 1)) { in tegra_i2c_xfer()
1400 dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len); in tegra_i2c_xfer()
1407 pm_runtime_put(i2c_dev->dev); in tegra_i2c_xfer()
1418 i2c_dev->atomic_mode = true; in tegra_i2c_xfer_atomic()
1420 i2c_dev->atomic_mode = false; in tegra_i2c_xfer_atomic()
1431 if (i2c_dev->hw->has_continue_xfer_support) in tegra_i2c_func()
1447 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1452 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1628 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1629 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1631 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
1633 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1634 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1635 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1636 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1637 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1639 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1647 struct device_node *np = i2c_dev->dev->of_node; in tegra_i2c_parse_dt()
1650 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); in tegra_i2c_parse_dt()
1652 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); in tegra_i2c_parse_dt()
1653 i2c_dev->multimaster_mode = multi_mode; in tegra_i2c_parse_dt()
1656 of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) in tegra_i2c_parse_dt()
1657 i2c_dev->is_dvc = true; in tegra_i2c_parse_dt()
1660 of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) in tegra_i2c_parse_dt()
1661 i2c_dev->is_vi = true; in tegra_i2c_parse_dt()
1666 if (ACPI_HANDLE(i2c_dev->dev)) in tegra_i2c_init_reset()
1669 i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); in tegra_i2c_init_reset()
1670 if (IS_ERR(i2c_dev->rst)) in tegra_i2c_init_reset()
1671 return dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), in tegra_i2c_init_reset()
1681 if (ACPI_HANDLE(i2c_dev->dev)) in tegra_i2c_init_clocks()
1684 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk"; in tegra_i2c_init_clocks()
1686 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw) in tegra_i2c_init_clocks()
1687 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk"; in tegra_i2c_init_clocks()
1690 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow"; in tegra_i2c_init_clocks()
1692 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks, in tegra_i2c_init_clocks()
1693 i2c_dev->clocks); in tegra_i2c_init_clocks()
1697 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_init_clocks()
1701 i2c_dev->div_clk = i2c_dev->clocks[0].clk; in tegra_i2c_init_clocks()
1703 if (!i2c_dev->multimaster_mode) in tegra_i2c_init_clocks()
1706 err = clk_enable(i2c_dev->div_clk); in tegra_i2c_init_clocks()
1708 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err); in tegra_i2c_init_clocks()
1715 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_init_clocks()
1722 if (i2c_dev->multimaster_mode) in tegra_i2c_release_clocks()
1723 clk_disable(i2c_dev->div_clk); in tegra_i2c_release_clocks()
1725 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_release_clocks()
1732 ret = pm_runtime_get_sync(i2c_dev->dev); in tegra_i2c_init_hardware()
1734 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret); in tegra_i2c_init_hardware()
1738 pm_runtime_put_sync(i2c_dev->dev); in tegra_i2c_init_hardware()
1749 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); in tegra_i2c_probe()
1751 return -ENOMEM; in tegra_i2c_probe()
1755 init_completion(&i2c_dev->msg_complete); in tegra_i2c_probe()
1756 init_completion(&i2c_dev->dma_complete); in tegra_i2c_probe()
1758 i2c_dev->hw = device_get_match_data(&pdev->dev); in tegra_i2c_probe()
1759 i2c_dev->cont_id = pdev->id; in tegra_i2c_probe()
1760 i2c_dev->dev = &pdev->dev; in tegra_i2c_probe()
1762 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in tegra_i2c_probe()
1763 if (IS_ERR(i2c_dev->base)) in tegra_i2c_probe()
1764 return PTR_ERR(i2c_dev->base); in tegra_i2c_probe()
1766 i2c_dev->base_phys = res->start; in tegra_i2c_probe()
1772 i2c_dev->irq = err; in tegra_i2c_probe()
1775 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); in tegra_i2c_probe()
1777 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq, in tegra_i2c_probe()
1780 dev_name(i2c_dev->dev), i2c_dev); in tegra_i2c_probe()
1799 * VI I2C is in VE power domain which is not always ON and not in tegra_i2c_probe()
1800 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a in tegra_i2c_probe()
1801 * non IRQ-safe domain because this prevents powering off the power in tegra_i2c_probe()
1804 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't in tegra_i2c_probe()
1807 if (!IS_VI(i2c_dev) && !has_acpi_companion(i2c_dev->dev)) in tegra_i2c_probe()
1808 pm_runtime_irq_safe(i2c_dev->dev); in tegra_i2c_probe()
1810 pm_runtime_enable(i2c_dev->dev); in tegra_i2c_probe()
1816 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); in tegra_i2c_probe()
1817 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node; in tegra_i2c_probe()
1818 i2c_dev->adapter.dev.parent = i2c_dev->dev; in tegra_i2c_probe()
1819 i2c_dev->adapter.retries = 1; in tegra_i2c_probe()
1820 i2c_dev->adapter.timeout = 6 * HZ; in tegra_i2c_probe()
1821 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; in tegra_i2c_probe()
1822 i2c_dev->adapter.owner = THIS_MODULE; in tegra_i2c_probe()
1823 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; in tegra_i2c_probe()
1824 i2c_dev->adapter.algo = &tegra_i2c_algo; in tegra_i2c_probe()
1825 i2c_dev->adapter.nr = pdev->id; in tegra_i2c_probe()
1826 ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev)); in tegra_i2c_probe()
1828 if (i2c_dev->hw->supports_bus_clear) in tegra_i2c_probe()
1829 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; in tegra_i2c_probe()
1831 strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), in tegra_i2c_probe()
1832 sizeof(i2c_dev->adapter.name)); in tegra_i2c_probe()
1834 err = i2c_add_numbered_adapter(&i2c_dev->adapter); in tegra_i2c_probe()
1841 pm_runtime_disable(i2c_dev->dev); in tegra_i2c_probe()
1854 i2c_del_adapter(&i2c_dev->adapter); in tegra_i2c_remove()
1855 pm_runtime_force_suspend(i2c_dev->dev); in tegra_i2c_remove()
1870 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_runtime_resume()
1875 * VI I2C device is attached to VE power domain which goes through in tegra_i2c_runtime_resume()
1877 * controller needs to be re-initialized after power ON. in tegra_i2c_runtime_resume()
1888 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_runtime_resume()
1897 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_runtime_suspend()
1907 i2c_mark_adapter_suspended(&i2c_dev->adapter); in tegra_i2c_suspend()
1946 i2c_mark_adapter_resumed(&i2c_dev->adapter); in tegra_i2c_resume()
1969 .name = "tegra-i2c",
1977 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver");