42 #define STM32F7_I2C_CR2				0x04  macro
815 	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_reload()
825 	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_reload()
845 	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_reload()
848 	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_reload()
895 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_xfer_msg()
967 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_xfer_msg()
983 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_xfer_msg()
1134 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_xfer_msg()
1146 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_rep_start()
1220 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_rep_start()
1300 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_start()
1318 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_start()
1462 			cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_slave_isr_event()
1464 			writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_slave_isr_event()
1467 			stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_isr_event()
1650 			stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_isr_event_thread()
1963 	stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);  in stm32f7_i2c_reg_slave()
2429 	backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_regs_backup()
2461 	writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_regs_restore()