Lines Matching +full:stop +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
9 * - Raw control of the SDA and SCK signals.
15 * - Atomic commands. A low level I2C symbol (such as generate
16 * start/stop/ack/nack bit, generate byte, receive byte, and receive
20 * This mode of operation is used by MODE_ATOMIC, which uses an I2C
22 * transactions using atomic mode commands, and also by MODE_SEQUENCE,
23 * which emits a simple fixed sequence of atomic mode commands.
29 * - Automatic mode. A bus address, and whether to read/write is
38 * Use of automatic mode and the FIFO can make much more efficient use
44 * the bus), MODE_ATOMIC must be used since automatic mode is normally
52 * Notice that the driver implements a timer-based timeout mechanism.
54 * received in automatic mode.
57 * each atomic mode command that gets completed. However, these events are
58 * not needed in automatic mode, becase those atomic mode commands are
62 * get the timer interrupt, as the timer is re-scheduled during FIFO
65 * In this way normal automatic mode operation isn't impacted by
262 * in the middle of the valid range (0-127).
304 /* Standard mode */
316 /* Fast mode */
337 /* Just issue a stop (after an abort condition) */
341 /* We're interested in different interrupts depending on the mode */
383 /* After the last transaction, wait for a stop bit */
387 enum img_i2c_mode mode; member
388 u32 int_enable; /* depends on mode */
392 * To avoid slave event interrupts in automatic mode, use a timer to
398 /* atomic mode state */
404 /* Sequence: either reset or stop. See img_i2c_sequence. */
407 /* raw mode */
416 writel(value, i2c->base + offset); in img_i2c_writel()
421 return readl(i2c->base + offset); in img_i2c_readl()
431 * The scb_wr_rd_fence() function does 2 dummy writes (to the read-only
438 if (i2c->need_wr_rd_fence) { in img_i2c_wr_rd_fence()
444 static void img_i2c_switch_mode(struct img_i2c *i2c, enum img_i2c_mode mode) in img_i2c_switch_mode() argument
446 i2c->mode = mode; in img_i2c_switch_mode()
447 i2c->int_enable = img_i2c_int_enable_by_mode[mode]; in img_i2c_switch_mode()
448 i2c->line_status = 0; in img_i2c_switch_mode()
453 i2c->raw_timeout = 0; in img_i2c_raw_op()
460 ((i2c->at_cur_cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) | in img_i2c_raw_op()
461 (i2c->at_cur_data << OVERRIDE_DATA_SHIFT)); in img_i2c_raw_op()
471 /* Send a single atomic mode command to the hardware */
474 i2c->at_cur_cmd = cmd; in img_i2c_atomic_op()
475 i2c->at_cur_data = data; in img_i2c_atomic_op()
478 if (cmd == CMD_GEN_DATA && i2c->mode == MODE_ATOMIC) { in img_i2c_atomic_op()
489 dev_dbg(i2c->adap.dev.parent, in img_i2c_atomic_op()
492 i2c->at_t_done = (cmd == CMD_RET_DATA || cmd == CMD_RET_ACK); in img_i2c_atomic_op()
493 i2c->at_slave_event = false; in img_i2c_atomic_op()
494 i2c->line_status = 0; in img_i2c_atomic_op()
503 /* Start a transaction in atomic mode */
507 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); in img_i2c_atomic_start()
513 i2c->t_halt = false; in img_i2c_soft_reset()
523 * every transfer but before the stop bit.
525 * release the transaction halt we have to re-enable it straight away
527 * all remaining bytes been processed and a stop bit being issued,
534 if (i2c->t_halt == t_halt) in img_i2c_transaction_halt()
536 i2c->t_halt = t_halt; in img_i2c_transaction_halt()
545 /* Drain data from the FIFO into the buffer (automatic mode) */
548 while (i2c->msg.len) { in img_i2c_read_fifo()
558 *i2c->msg.buf = data; in img_i2c_read_fifo()
561 i2c->msg.len--; in img_i2c_read_fifo()
562 i2c->msg.buf++; in img_i2c_read_fifo()
566 /* Fill the FIFO with data from the buffer (automatic mode) */
569 while (i2c->msg.len) { in img_i2c_write_fifo()
577 img_i2c_writel(i2c, SCB_WRITE_DATA_REG, *i2c->msg.buf); in img_i2c_write_fifo()
578 i2c->msg.len--; in img_i2c_write_fifo()
579 i2c->msg.buf++; in img_i2c_write_fifo()
583 if (!i2c->msg.len) in img_i2c_write_fifo()
584 i2c->int_enable &= ~INT_FIFO_EMPTYING; in img_i2c_write_fifo()
587 /* Start a read transaction in automatic mode */
591 if (!i2c->last_msg) in img_i2c_read()
592 i2c->int_enable |= INT_SLAVE_EVENT; in img_i2c_read()
594 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); in img_i2c_read()
595 img_i2c_writel(i2c, SCB_READ_ADDR_REG, i2c->msg.addr); in img_i2c_read()
596 img_i2c_writel(i2c, SCB_READ_COUNT_REG, i2c->msg.len); in img_i2c_read()
598 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); in img_i2c_read()
601 /* Start a write transaction in automatic mode */
605 if (!i2c->last_msg) in img_i2c_write()
606 i2c->int_enable |= INT_SLAVE_EVENT; in img_i2c_write()
608 img_i2c_writel(i2c, SCB_WRITE_ADDR_REG, i2c->msg.addr); in img_i2c_write()
609 img_i2c_writel(i2c, SCB_WRITE_COUNT_REG, i2c->msg.len); in img_i2c_write()
611 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); in img_i2c_write()
615 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); in img_i2c_write()
627 i2c->msg_status = status; in img_i2c_complete_transaction()
630 complete(&i2c->msg_complete); in img_i2c_complete_transaction()
636 /* Stay in raw mode for this, so we don't just loop infinitely */ in img_i2c_raw_atomic_delay_handler()
637 img_i2c_atomic_op(i2c, i2c->at_cur_cmd, i2c->at_cur_data); in img_i2c_raw_atomic_delay_handler()
646 if (i2c->raw_timeout == 0) in img_i2c_raw()
649 --i2c->raw_timeout; in img_i2c_raw()
663 int next_cmd = -1; in img_i2c_sequence()
667 i2c->at_slave_event = true; in img_i2c_sequence()
669 i2c->at_t_done = true; in img_i2c_sequence()
671 if (!i2c->at_slave_event || !i2c->at_t_done) in img_i2c_sequence()
675 if (i2c->at_cur_cmd >= 0 && in img_i2c_sequence()
676 i2c->at_cur_cmd < ARRAY_SIZE(continue_bits)) { in img_i2c_sequence()
677 unsigned int cont_bits = continue_bits[i2c->at_cur_cmd]; in img_i2c_sequence()
681 if (!(i2c->line_status & cont_bits)) in img_i2c_sequence()
686 /* follow the sequence of commands in i2c->seq */ in img_i2c_sequence()
687 next_cmd = *i2c->seq; in img_i2c_sequence()
688 /* stop on a nil */ in img_i2c_sequence()
695 ++i2c->seq; in img_i2c_sequence()
696 next_data = *i2c->seq; in img_i2c_sequence()
698 ++i2c->seq; in img_i2c_sequence()
708 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); in img_i2c_reset_start()
709 i2c->seq = img_i2c_reset_seq; in img_i2c_reset_start()
710 i2c->at_slave_event = true; in img_i2c_reset_start()
711 i2c->at_t_done = true; in img_i2c_reset_start()
712 i2c->at_cur_cmd = -1; in img_i2c_reset_start()
720 /* Initiate a stop bit sequence */ in img_i2c_stop_start()
722 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); in img_i2c_stop_start()
723 i2c->seq = img_i2c_stop_seq; in img_i2c_stop_start()
724 i2c->at_slave_event = true; in img_i2c_stop_start()
725 i2c->at_t_done = true; in img_i2c_stop_start()
726 i2c->at_cur_cmd = -1; in img_i2c_stop_start()
736 int next_cmd = -1; in img_i2c_atomic()
740 i2c->at_slave_event = true; in img_i2c_atomic()
742 i2c->at_t_done = true; in img_i2c_atomic()
744 if (!i2c->at_slave_event || !i2c->at_t_done) in img_i2c_atomic()
746 if (i2c->line_status & LINESTAT_ABORT_DET) { in img_i2c_atomic()
747 dev_dbg(i2c->adap.dev.parent, "abort condition detected\n"); in img_i2c_atomic()
749 i2c->msg_status = -EIO; in img_i2c_atomic()
753 /* i2c->at_cur_cmd may have completed */ in img_i2c_atomic()
754 switch (i2c->at_cur_cmd) { in img_i2c_atomic()
757 next_data = i2c_8bit_addr_from_msg(&i2c->msg); in img_i2c_atomic()
760 if (i2c->line_status & LINESTAT_INPUT_HELD_V) in img_i2c_atomic()
764 if (i2c->line_status & LINESTAT_ACK_DET || in img_i2c_atomic()
765 (i2c->line_status & LINESTAT_NACK_DET && in img_i2c_atomic()
766 i2c->msg.flags & I2C_M_IGNORE_NAK)) { in img_i2c_atomic()
767 if (i2c->msg.len == 0) { in img_i2c_atomic()
769 } else if (i2c->msg.flags & I2C_M_RD) { in img_i2c_atomic()
773 next_data = *i2c->msg.buf; in img_i2c_atomic()
774 --i2c->msg.len; in img_i2c_atomic()
775 ++i2c->msg.buf; in img_i2c_atomic()
777 } else if (i2c->line_status & LINESTAT_NACK_DET) { in img_i2c_atomic()
778 i2c->msg_status = -EIO; in img_i2c_atomic()
783 if (i2c->line_status & LINESTAT_INPUT_HELD_V) { in img_i2c_atomic()
784 *i2c->msg.buf = (i2c->line_status & in img_i2c_atomic()
787 --i2c->msg.len; in img_i2c_atomic()
788 ++i2c->msg.buf; in img_i2c_atomic()
789 if (i2c->msg.len) in img_i2c_atomic()
796 if (i2c->line_status & LINESTAT_ACK_DET) { in img_i2c_atomic()
799 i2c->msg_status = -EIO; in img_i2c_atomic()
810 dev_err(i2c->adap.dev.parent, "bad atomic command %d\n", in img_i2c_atomic()
811 i2c->at_cur_cmd); in img_i2c_atomic()
812 i2c->msg_status = -EIO; in img_i2c_atomic()
818 if (next_cmd != -1) { in img_i2c_atomic()
819 /* don't actually stop unless we're the last transaction */ in img_i2c_atomic()
820 if (next_cmd == CMD_GEN_STOP && !i2c->msg_status && in img_i2c_atomic()
821 !i2c->last_msg) in img_i2c_atomic()
829 * Timer function to check if something has gone wrong in automatic mode (so we
838 spin_lock_irqsave(&i2c->lock, flags); in img_i2c_check_timer()
843 dev_dbg(i2c->adap.dev.parent, in img_i2c_check_timer()
847 i2c->int_enable | INT_SLAVE_EVENT); in img_i2c_check_timer()
850 spin_unlock_irqrestore(&i2c->lock, flags); in img_i2c_check_timer()
861 dev_dbg(i2c->adap.dev.parent, "abort condition detected\n"); in img_i2c_auto()
863 if ((i2c->msg.flags & I2C_M_RD) && in img_i2c_auto()
866 /* use atomic mode and try to force a stop bit */ in img_i2c_auto()
867 i2c->msg_status = -EIO; in img_i2c_auto()
873 if (!i2c->last_msg && line_status & LINESTAT_START_BIT_DET) { in img_i2c_auto()
874 img_i2c_transaction_halt(i2c, !i2c->last_msg); in img_i2c_auto()
876 i2c->int_enable &= ~INT_SLAVE_EVENT; in img_i2c_auto()
879 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); in img_i2c_auto()
883 if (i2c->msg.flags & I2C_M_RD) in img_i2c_auto()
888 if (i2c->msg.flags & I2C_M_RD) { in img_i2c_auto()
891 if (i2c->msg.len == 0) in img_i2c_auto()
897 i2c->msg.len == 0) in img_i2c_auto()
908 img_i2c_transaction_halt(i2c, !i2c->last_msg); in img_i2c_auto()
938 spin_lock(&i2c->lock); in img_i2c_isr()
941 i2c->line_status &= ~LINESTAT_INPUT_DATA; in img_i2c_isr()
942 i2c->line_status |= line_status; in img_i2c_isr()
952 dev_crit(i2c->adap.dev.parent, in img_i2c_isr()
954 (i2c->msg.flags & I2C_M_RD) ? "reading" : "writing", in img_i2c_isr()
955 i2c->msg.addr); in img_i2c_isr()
960 if (i2c->mode == MODE_ATOMIC) in img_i2c_isr()
962 else if (i2c->mode == MODE_AUTOMATIC) in img_i2c_isr()
964 else if (i2c->mode == MODE_SEQUENCE) in img_i2c_isr()
966 else if (i2c->mode == MODE_WAITSTOP && (int_status & INT_SLAVE_EVENT) && in img_i2c_isr()
969 else if (i2c->mode == MODE_RAW) in img_i2c_isr()
980 * Only wait for stop on last message. in img_i2c_isr()
981 * Also we may already have detected the stop bit. in img_i2c_isr()
983 if (!i2c->last_msg || i2c->line_status & LINESTAT_STOP_BIT_DET) in img_i2c_isr()
991 int status = -(hret & ISR_STATUS_M); in img_i2c_isr()
998 /* Enable interrupts (int_enable may be altered by changing mode) */ in img_i2c_isr()
999 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); in img_i2c_isr()
1001 spin_unlock(&i2c->lock); in img_i2c_isr()
1012 spin_lock_irqsave(&i2c->lock, flags); in img_i2c_reset_bus()
1013 reinit_completion(&i2c->msg_complete); in img_i2c_reset_bus()
1015 spin_unlock_irqrestore(&i2c->lock, flags); in img_i2c_reset_bus()
1017 time_left = wait_for_completion_timeout(&i2c->msg_complete, in img_i2c_reset_bus()
1020 return -ETIMEDOUT; in img_i2c_reset_bus()
1032 if (i2c->mode == MODE_SUSPEND) { in img_i2c_xfer()
1034 return -EIO; in img_i2c_xfer()
1037 if (i2c->mode == MODE_FATAL) in img_i2c_xfer()
1038 return -EIO; in img_i2c_xfer()
1043 * and pull the data line low, preventing a stop bit. in img_i2c_xfer()
1046 return -EIO; in img_i2c_xfer()
1049 * cannot do them in automatic mode, so use atomic mode in img_i2c_xfer()
1052 * Also, the I2C_M_IGNORE_NAK mode can only be implemented in img_i2c_xfer()
1053 * in atomic mode. in img_i2c_xfer()
1060 ret = pm_runtime_resume_and_get(adap->dev.parent); in img_i2c_xfer()
1068 spin_lock_irqsave(&i2c->lock, flags); in img_i2c_xfer()
1072 * original or we'll confuse drivers and i2c-dev. in img_i2c_xfer()
1074 i2c->msg = *msg; in img_i2c_xfer()
1075 i2c->msg_status = 0; in img_i2c_xfer()
1078 * After the last message we must have waited for a stop bit. in img_i2c_xfer()
1080 * before the stop bit is sent, and the linux I2C interface in img_i2c_xfer()
1084 i2c->last_msg = (i == num - 1); in img_i2c_xfer()
1085 reinit_completion(&i2c->msg_complete); in img_i2c_xfer()
1103 img_i2c_transaction_halt(i2c, !i2c->last_msg); in img_i2c_xfer()
1105 if (msg->flags & I2C_M_RD) in img_i2c_xfer()
1119 img_i2c_transaction_halt(i2c, !i2c->last_msg); in img_i2c_xfer()
1121 spin_unlock_irqrestore(&i2c->lock, flags); in img_i2c_xfer()
1123 time_left = wait_for_completion_timeout(&i2c->msg_complete, in img_i2c_xfer()
1125 del_timer_sync(&i2c->check_timer); in img_i2c_xfer()
1128 i2c->msg_status = -ETIMEDOUT; in img_i2c_xfer()
1130 if (i2c->msg_status) in img_i2c_xfer()
1134 pm_runtime_mark_last_busy(adap->dev.parent); in img_i2c_xfer()
1135 pm_runtime_put_autosuspend(adap->dev.parent); in img_i2c_xfer()
1137 return i2c->msg_status ? i2c->msg_status : num; in img_i2c_xfer()
1158 ret = pm_runtime_resume_and_get(i2c->adap.dev.parent); in img_i2c_init()
1164 dev_info(i2c->adap.dev.parent, in img_i2c_init()
1168 pm_runtime_mark_last_busy(i2c->adap.dev.parent); in img_i2c_init()
1169 pm_runtime_put_autosuspend(i2c->adap.dev.parent); in img_i2c_init()
1170 return -EINVAL; in img_i2c_init()
1174 i2c->need_wr_rd_fence = true; in img_i2c_init()
1176 /* Determine what mode we're in from the bitrate */ in img_i2c_init()
1179 if (i2c->bitrate <= timings[i].max_bitrate) { in img_i2c_init()
1184 if (i2c->bitrate > timings[ARRAY_SIZE(timings) - 1].max_bitrate) { in img_i2c_init()
1185 dev_warn(i2c->adap.dev.parent, in img_i2c_init()
1187 i2c->bitrate, in img_i2c_init()
1188 timings[ARRAY_SIZE(timings) - 1].max_bitrate); in img_i2c_init()
1189 timing = timings[ARRAY_SIZE(timings) - 1]; in img_i2c_init()
1190 i2c->bitrate = timing.max_bitrate; in img_i2c_init()
1193 bitrate_khz = i2c->bitrate / 1000; in img_i2c_init()
1194 clk_khz = clk_get_rate(i2c->scb_clk) / 1000; in img_i2c_init()
1209 * If it's between the 20-40 MHz range, there's no need to divide in img_i2c_init()
1229 data = filt | ((inc & SCB_INC_MASK) << SCB_INC_SHIFT) | (prescale - 1); in img_i2c_init()
1246 tckl = int_bitrate - tckh; in img_i2c_init()
1253 tckh = int_bitrate - tckl; in img_i2c_init()
1257 --tckh; in img_i2c_init()
1260 --tckl; in img_i2c_init()
1269 data = tsdh - 1; in img_i2c_init()
1280 --data; in img_i2c_init()
1286 --data; in img_i2c_init()
1295 --data; in img_i2c_init()
1315 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); in img_i2c_init()
1320 pm_runtime_mark_last_busy(i2c->adap.dev.parent); in img_i2c_init()
1321 pm_runtime_put_autosuspend(i2c->adap.dev.parent); in img_i2c_init()
1328 struct device_node *node = pdev->dev.of_node; in img_i2c_probe()
1333 i2c = devm_kzalloc(&pdev->dev, sizeof(struct img_i2c), GFP_KERNEL); in img_i2c_probe()
1335 return -ENOMEM; in img_i2c_probe()
1337 i2c->base = devm_platform_ioremap_resource(pdev, 0); in img_i2c_probe()
1338 if (IS_ERR(i2c->base)) in img_i2c_probe()
1339 return PTR_ERR(i2c->base); in img_i2c_probe()
1345 i2c->sys_clk = devm_clk_get(&pdev->dev, "sys"); in img_i2c_probe()
1346 if (IS_ERR(i2c->sys_clk)) { in img_i2c_probe()
1347 dev_err(&pdev->dev, "can't get system clock\n"); in img_i2c_probe()
1348 return PTR_ERR(i2c->sys_clk); in img_i2c_probe()
1351 i2c->scb_clk = devm_clk_get(&pdev->dev, "scb"); in img_i2c_probe()
1352 if (IS_ERR(i2c->scb_clk)) { in img_i2c_probe()
1353 dev_err(&pdev->dev, "can't get core clock\n"); in img_i2c_probe()
1354 return PTR_ERR(i2c->scb_clk); in img_i2c_probe()
1357 ret = devm_request_irq(&pdev->dev, irq, img_i2c_isr, 0, in img_i2c_probe()
1358 pdev->name, i2c); in img_i2c_probe()
1360 dev_err(&pdev->dev, "can't request irq %d\n", irq); in img_i2c_probe()
1365 timer_setup(&i2c->check_timer, img_i2c_check_timer, 0); in img_i2c_probe()
1367 i2c->bitrate = timings[0].max_bitrate; in img_i2c_probe()
1368 if (!of_property_read_u32(node, "clock-frequency", &val)) in img_i2c_probe()
1369 i2c->bitrate = val; in img_i2c_probe()
1371 i2c_set_adapdata(&i2c->adap, i2c); in img_i2c_probe()
1372 i2c->adap.dev.parent = &pdev->dev; in img_i2c_probe()
1373 i2c->adap.dev.of_node = node; in img_i2c_probe()
1374 i2c->adap.owner = THIS_MODULE; in img_i2c_probe()
1375 i2c->adap.algo = &img_i2c_algo; in img_i2c_probe()
1376 i2c->adap.retries = 5; in img_i2c_probe()
1377 i2c->adap.nr = pdev->id; in img_i2c_probe()
1378 snprintf(i2c->adap.name, sizeof(i2c->adap.name), "IMG SCB I2C"); in img_i2c_probe()
1381 spin_lock_init(&i2c->lock); in img_i2c_probe()
1382 init_completion(&i2c->msg_complete); in img_i2c_probe()
1386 pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_I2C_PM_TIMEOUT); in img_i2c_probe()
1387 pm_runtime_use_autosuspend(&pdev->dev); in img_i2c_probe()
1388 pm_runtime_enable(&pdev->dev); in img_i2c_probe()
1389 if (!pm_runtime_enabled(&pdev->dev)) { in img_i2c_probe()
1390 ret = img_i2c_runtime_resume(&pdev->dev); in img_i2c_probe()
1399 ret = i2c_add_numbered_adapter(&i2c->adap); in img_i2c_probe()
1406 if (!pm_runtime_enabled(&pdev->dev)) in img_i2c_probe()
1407 img_i2c_runtime_suspend(&pdev->dev); in img_i2c_probe()
1408 pm_runtime_disable(&pdev->dev); in img_i2c_probe()
1409 pm_runtime_dont_use_autosuspend(&pdev->dev); in img_i2c_probe()
1417 i2c_del_adapter(&i2c->adap); in img_i2c_remove()
1418 pm_runtime_disable(&dev->dev); in img_i2c_remove()
1419 if (!pm_runtime_status_suspended(&dev->dev)) in img_i2c_remove()
1420 img_i2c_runtime_suspend(&dev->dev); in img_i2c_remove()
1427 clk_disable_unprepare(i2c->scb_clk); in img_i2c_runtime_suspend()
1428 clk_disable_unprepare(i2c->sys_clk); in img_i2c_runtime_suspend()
1438 ret = clk_prepare_enable(i2c->sys_clk); in img_i2c_runtime_resume()
1444 ret = clk_prepare_enable(i2c->scb_clk); in img_i2c_runtime_resume()
1447 clk_disable_unprepare(i2c->sys_clk); in img_i2c_runtime_resume()
1488 { .compatible = "img,scb-i2c" },
1495 .name = "img-i2c-scb",