Lines Matching +full:0 +full:x0210

12 	REG_MSU_MSUPARAMS	= 0x0000,
13 	REG_MSU_MSUSTS		= 0x0008,
14 	REG_MSU_MINTCTL		= 0x0004, /* MSU-global interrupt control */
15 	REG_MSU_MSC0CTL		= 0x0100, /* MSC0 control */
16 	REG_MSU_MSC0STS		= 0x0104, /* MSC0 status */
17 	REG_MSU_MSC0BAR		= 0x0108, /* MSC0 output base address */
18 	REG_MSU_MSC0SIZE	= 0x010c, /* MSC0 output size */
19 	REG_MSU_MSC0MWP		= 0x0110, /* MSC0 write pointer */
20 	REG_MSU_MSC0NWSA	= 0x011c, /* MSC0 next window start address */
22 	REG_MSU_MSC1CTL		= 0x0200, /* MSC1 control */
23 	REG_MSU_MSC1STS		= 0x0204, /* MSC1 status */
24 	REG_MSU_MSC1BAR		= 0x0208, /* MSC1 output base address */
25 	REG_MSU_MSC1SIZE	= 0x020c, /* MSC1 output size */
26 	REG_MSU_MSC1MWP		= 0x0210, /* MSC1 write pointer */
27 	REG_MSU_MSC1NWSA	= 0x021c, /* MSC1 next window start address */
31 #define MSUSTS_MSU_INT	BIT(0)
36 #define MSC_EN		BIT(0)
43 #define MICDE		BIT(0)
71 #define MSC_SW_TAG_LASTBLK	BIT(0)
75 #define MSC_HW_TAG_TRIGGER	BIT(0)
83 		return 0;  in msc_data_sz()