hwtracing/coresight/coresight-tpiu.c

24 #define TPIU_SUPP_PORTSZ	0x000
25 #define TPIU_CURR_PORTSZ	0x004
26 #define TPIU_SUPP_TRIGMODES	0x100
27 #define TPIU_TRIG_CNTRVAL	0x104
28 #define TPIU_TRIG_MULT		0x108
29 #define TPIU_SUPP_TESTPATM	0x200
30 #define TPIU_CURR_TESTPATM	0x204
31 #define TPIU_TEST_PATREPCNTR	0x208
32 #define TPIU_FFSR		0x300
33 #define TPIU_FFCR		0x304
34 #define TPIU_FSYNC_CNTR		0x308
35 #define TPIU_EXTCTL_INPORT	0x400
36 #define TPIU_EXTCTL_OUTPORT	0x404
37 #define TPIU_ITTRFLINACK	0xee4
38 #define TPIU_ITTRFLIN		0xee8
39 #define TPIU_ITATBDATA0		0xeec
40 #define TPIU_ITATBCTR2		0xef0
41 #define TPIU_ITATBCTR1		0xef4
42 #define TPIU_ITATBCTR0		0xef8
45 /* FFSR - 0x300 */
47 /* FFCR - 0x304 */
86 	return 0;  in tpiu_enable()
98 	coresight_timeout(csa, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);  in tpiu_disable_hw()
117 	return 0;  in tpiu_disable()
135 	struct coresight_desc desc = { 0 };  in __tpiu_probe()
183 		return 0;  in __tpiu_probe()
220 	return 0;  in tpiu_runtime_suspend()
232 	return 0;  in tpiu_runtime_resume()
242 		.id	= 0x000bb912,
243 		.mask	= 0x000fffff,
246 		.id	= 0x0004b912,
247 		.mask	= 0x0007ffff,
251 		.id	= 0x000bb9e7,
252 		.mask	= 0x000fffff,
254 	{ 0, 0, NULL },
272 	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in tpiu_platform_probe()
302 	{"ARMHC979", 0, 0, 0}, /* ARM CoreSight TPIU */