Lines Matching +full:0 +full:xee0
16 #define TMC_RSZ 0x004
17 #define TMC_STS 0x00c
18 #define TMC_RRD 0x010
19 #define TMC_RRP 0x014
20 #define TMC_RWP 0x018
21 #define TMC_TRG 0x01c
22 #define TMC_CTL 0x020
23 #define TMC_RWD 0x024
24 #define TMC_MODE 0x028
25 #define TMC_LBUFLEVEL 0x02c
26 #define TMC_CBUFLEVEL 0x030
27 #define TMC_BUFWM 0x034
28 #define TMC_RRPHI 0x038
29 #define TMC_RWPHI 0x03c
30 #define TMC_AXICTL 0x110
31 #define TMC_DBALO 0x118
32 #define TMC_DBAHI 0x11c
33 #define TMC_FFSR 0x300
34 #define TMC_FFCR 0x304
35 #define TMC_PSCR 0x308
36 #define TMC_ITMISCOP0 0xee0
37 #define TMC_ITTRFLIN 0xee8
38 #define TMC_ITATBDATA0 0xeec
39 #define TMC_ITATBCTR2 0xef0
40 #define TMC_ITATBCTR1 0xef4
41 #define TMC_ITATBCTR0 0xef8
42 #define TMC_AUTHSTATUS 0xfb8
45 /* TMC_CTL - 0x020 */
46 #define TMC_CTL_CAPT_EN BIT(0)
47 /* TMC_STS - 0x00C */
49 #define TMC_STS_FULL BIT(0)
53 * TMC_AXICTL - 0x110
56 * Bits [0-1] : ProtCtrlBit0-1
57 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE)
67 #define TMC_AXICTL_CLEAR_MASK 0xfbf
68 #define TMC_AXICTL_ARCACHE_MASK (0xf << 16)
70 #define TMC_AXICTL_PROT_CTL_B0 BIT(0)
73 #define TMC_AXICTL_WR_BURST(v) (((v) & 0xf) << 8)
74 #define TMC_AXICTL_WR_BURST_16 0xf
76 #define TMC_AXICTL_AXCACHE_OS (0xf << 2)
77 #define TMC_AXICTL_ARCACHE_OS (0xf << 16)
79 /* TMC_FFCR - 0x304 */
81 #define TMC_FFCR_EN_FMT BIT(0)
93 #define TMC_DEVID_AXIAW_MASK 0x7f
95 #define TMC_AUTH_NSID_MASK GENMASK(1, 0)
117 #define TMC_ETR_SG (0x1U << 0)
119 #define TMC_ETR_AXI_ARCACHE (0x1U << 1)
128 #define TMC_ETR_SAVE_RESTORE (0x1U << 2)