Lines Matching defs:etmv4_config
819 struct etmv4_config { struct
820 u32 mode;
821 u32 pe_sel;
822 u32 cfg;
823 u32 eventctrl0;
824 u32 eventctrl1;
825 u32 stall_ctrl;
826 u32 ts_ctrl;
827 u32 syncfreq;
828 u32 ccctlr;
829 u32 bb_ctrl;
830 u32 vinst_ctrl;
831 u32 viiectlr;
832 u32 vissctlr;
833 u32 vipcssctlr;
834 u8 seq_idx;
835 u32 seq_ctrl[ETM_MAX_SEQ_STATES];
836 u32 seq_rst;
837 u32 seq_state;
838 u8 cntr_idx;
839 u32 cntrldvr[ETMv4_MAX_CNTR];
840 u32 cntr_ctrl[ETMv4_MAX_CNTR];
841 u32 cntr_val[ETMv4_MAX_CNTR];
842 u8 res_idx;
843 u32 res_ctrl[ETM_MAX_RES_SEL];
844 u8 ss_idx;
845 u32 ss_ctrl[ETM_MAX_SS_CMP];
846 u32 ss_status[ETM_MAX_SS_CMP];
847 u32 ss_pe_cmp[ETM_MAX_SS_CMP];
848 u8 addr_idx;
849 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
850 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
851 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
852 u8 ctxid_idx;
853 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
854 u32 ctxid_mask0;
855 u32 ctxid_mask1;
856 u8 vmid_idx;
857 u64 vmid_val[ETM_MAX_VMID_CMP];
858 u32 vmid_mask0;
859 u32 vmid_mask1;
860 u32 ext_inp;
861 u8 s_ex_level;