Lines Matching +full:0 +full:x1e8
15 * 0x000 - 0x2FC: Trace registers
16 * 0x300 - 0x314: Management registers
17 * 0x318 - 0xEFC: Trace registers
20 * 0xF00 - 0xF9C: Management registers
21 * 0xFA0 - 0xFA4: Management registers in PFTv1.0
23 * 0xFA8 - 0xFFC: Management registers
26 /* Trace registers (0x000-0x2FC) */
27 #define ETMCR 0x000
28 #define ETMCCR 0x004
29 #define ETMTRIGGER 0x008
30 #define ETMSR 0x010
31 #define ETMSCR 0x014
32 #define ETMTSSCR 0x018
33 #define ETMTECR2 0x01c
34 #define ETMTEEVR 0x020
35 #define ETMTECR1 0x024
36 #define ETMFFLR 0x02c
37 #define ETMACVRn(n) (0x040 + (n * 4))
38 #define ETMACTRn(n) (0x080 + (n * 4))
39 #define ETMCNTRLDVRn(n) (0x140 + (n * 4))
40 #define ETMCNTENRn(n) (0x150 + (n * 4))
41 #define ETMCNTRLDEVRn(n) (0x160 + (n * 4))
42 #define ETMCNTVRn(n) (0x170 + (n * 4))
43 #define ETMSQ12EVR 0x180
44 #define ETMSQ21EVR 0x184
45 #define ETMSQ23EVR 0x188
46 #define ETMSQ31EVR 0x18c
47 #define ETMSQ32EVR 0x190
48 #define ETMSQ13EVR 0x194
49 #define ETMSQR 0x19c
50 #define ETMEXTOUTEVRn(n) (0x1a0 + (n * 4))
51 #define ETMCIDCVRn(n) (0x1b0 + (n * 4))
52 #define ETMCIDCMR 0x1bc
53 #define ETMIMPSPEC0 0x1c0
54 #define ETMIMPSPEC1 0x1c4
55 #define ETMIMPSPEC2 0x1c8
56 #define ETMIMPSPEC3 0x1cc
57 #define ETMIMPSPEC4 0x1d0
58 #define ETMIMPSPEC5 0x1d4
59 #define ETMIMPSPEC6 0x1d8
60 #define ETMIMPSPEC7 0x1dc
61 #define ETMSYNCFR 0x1e0
62 #define ETMIDR 0x1e4
63 #define ETMCCER 0x1e8
64 #define ETMEXTINSELR 0x1ec
65 #define ETMTESSEICR 0x1f0
66 #define ETMEIBCR 0x1f4
67 #define ETMTSEVR 0x1f8
68 #define ETMAUXCR 0x1fc
69 #define ETMTRACEIDR 0x200
70 #define ETMVMIDCVR 0x240
71 /* Management registers (0x300-0x314) */
72 #define ETMOSLAR 0x300
73 #define ETMOSLSR 0x304
74 #define ETMOSSRR 0x308
75 #define ETMPDCR 0x310
76 #define ETMPDSR 0x314
82 /* ETMCR - 0x00 */
83 #define ETMCR_PWD_DWN BIT(0)
92 /* ETMCCR - 0x04 */
94 /* ETMPDCR - 0x310 */
96 /* ETMTECR1 - 0x024 */
97 #define ETMTECR1_ADDR_COMP_1 BIT(0)
100 /* ETMCCER - 0x1E8 */
104 #define ETM_MODE_EXCLUDE BIT(0)
117 #define ETM_SQR_MASK 0x3
118 #define ETM_TRACEID_MASK 0x3f
119 #define ETM_EVENT_MASK 0x1ffff
120 #define ETM_SYNC_MASK 0xfff
121 #define ETM_ALL_MASK 0xffffffff
124 #define ETM_SEQ_STATE_MAX_VAL (0x2)
128 ((0x0f << 0) | \
130 (0x06 << 4))
133 ((0x00 << 7) | \
135 (0x00 << 11))