Lines Matching +full:0 +full:x144

22  * 0x000 - 0x144: CTI programming and status
23  * 0xEDC - 0xEF8: CTI integration test.
24  * 0xF00 - 0xFFC: Coresight management registers.
27 #define CTICONTROL		0x000
28 #define CTIINTACK		0x010
29 #define CTIAPPSET		0x014
30 #define CTIAPPCLEAR		0x018
31 #define CTIAPPPULSE		0x01C
32 #define CTIINEN(n)		(0x020 + (4 * n))
33 #define CTIOUTEN(n)		(0x0A0 + (4 * n))
34 #define CTITRIGINSTATUS		0x130
35 #define CTITRIGOUTSTATUS	0x134
36 #define CTICHINSTATUS		0x138
37 #define CTICHOUTSTATUS		0x13C
38 #define CTIGATE			0x140
39 #define ASICCTL			0x144
41 #define ITCHINACK		0xEDC /* WO CTI CSSoc 400 only*/
42 #define ITTRIGINACK		0xEE0 /* WO CTI CSSoc 400 only*/
43 #define ITCHOUT			0xEE4 /* WO RW-600 */
44 #define ITTRIGOUT		0xEE8 /* WO RW-600 */
45 #define ITCHOUTACK		0xEEC /* RO CTI CSSoc 400 only*/
46 #define ITTRIGOUTACK		0xEF0 /* RO CTI CSSoc 400 only*/
47 #define ITCHIN			0xEF4 /* RO */
48 #define ITTRIGIN		0xEF8 /* RO */
50 #define CTIDEVAFF0		0xFA8
51 #define CTIDEVAFF1		0xFAC
101  *          assumed there is a single CTM per SoC, ID 0).