Lines Matching +full:trace +full:- +full:buffer +full:- +full:extension

1 # SPDX-License-Identifier: GPL-2.0-only
14 	  and trace drivers to register themselves with. It's intended to build
17 	  trace source gets enabled.
27 	  responsible for transporting and collecting the trace data
28 	  respectively.  Link and sinks are dynamically aggregated with a trace
29 	  entity at run time to form a complete trace path.
32 	  modules will be called coresight-funnel and coresight-replicator.
39 	  This enables support for the Trace Memory Controller driver.
41 	  trace router - ETR) or sink (embedded trace FIFO).  The driver
46 	  module will be called coresight-tmc.
54 	   lookup. CATU helps TMC ETR to use a large physically non-contiguous trace
55 	   buffer by translating the addresses used by ETR to the physical address
56 	   by looking up the provided table. CATU can also be used in pass-through
60 	   module will be called coresight-catu.
66 	  This enables support for the Trace Port Interface Unit driver,
67 	  responsible for bridging the gap between the on-chip coresight
68 	  components and a trace for bridging the gap between the on-chip
69 	  coresight components and a trace port collection engine, typically
71 	  the on-board coresight memory can handle.
74 	  module will be called coresight-tpiu.
80 	  This enables support for the Embedded Trace Buffer version 1.0 driver
85 	  module will be called coresight-etb10.
88 	tristate "CoreSight Embedded Trace Macrocell 3.x driver"
98 	  module will be called coresight-etm3x.
106 	  This driver provides support for the CoreSight Embedded Trace Macrocell
107 	  version 4.x and the Embedded Trace Extensions (ETE). Both are CPU tracer
112 	  module will be called coresight-etm4x.
123 	tristate "CoreSight System Trace Macrocell driver"
134 	  module will be called coresight-stm.
142 	  is primarily used to dump sample-based profiling registers when
147 	  properly, please refer Documentation/trace/coresight/coresight-cpu-debug.rst
151 	  module will be called coresight-cpu-debug.
157 	  Say Y here to enable the CoreSight Debug panic-debug by default. This
171 	  These provide hardware triggering events between CoreSight trace
172 	  source and sink components. These can be used to halt trace or
173 	  inject events into the trace stream. CTI also provides a software
174 	  control to trigger the same halt events. This can provide fast trace
179 	  module will be called coresight-cti.
192 	tristate "Trace Buffer Extension (TRBE) driver"
195 	  This driver provides support for percpu Trace Buffer Extension (TRBE).
197 	  component. ETE generates trace data which is then captured with TRBE.
199 	  system registers. But its explicit dependency with trace unit (ETE)
203 	  called coresight-trbe.
206 	tristate "Ultrasoc system memory buffer drivers"
210 	  This driver provides support for the Ultrasoc system memory buffer (SMB).
211 	  SMB is responsible for receiving the trace data from Coresight ETM devices
212 	  and storing them to a system buffer.
215 	  called ultrasoc-smb.
218 	tristate "CoreSight Trace, Profiling & Diagnostics Monitor driver"
227 	  called coresight-tpdm.
230 	tristate "CoreSight Trace, Profiling & Diagnostics Aggregator driver"
238 	  called coresight-tpda.
245 	  other subsystem and use Linux drivers to configure rest of trace
249 	  called coresight-dummy.