16  * w83627hf	9	3	2	3	0x20	0x5ca3	no	yes(LPC)
17  * w83627thf	7	3	3	3	0x90	0x5ca3	no	yes(LPC)
18  * w83637hf	7	3	3	3	0x80	0x5ca3	no	yes(LPC)
19  * w83687thf	7	3	3	3	0x90	0x5ca3	no	yes(LPC)
20  * w83697hf	8	2	2	2	0x60	0x5ca3	no	yes(LPC)
56 static u8 force_i2c = 0x1f;
57 module_param(force_i2c, byte, 0);
62 module_param(init, bool, 0);
66 module_param(force_id, ushort, 0);
70 #define DEV			0x07 /* Register: Logical device select */
73 #define W83627HF_LD_FDC		0x00
74 #define W83627HF_LD_PRT		0x01
75 #define W83627HF_LD_UART1	0x02
76 #define W83627HF_LD_UART2	0x03
77 #define W83627HF_LD_KBC		0x05
78 #define W83627HF_LD_CIR		0x06 /* w83627hf only */
79 #define W83627HF_LD_GAME	0x07
80 #define W83627HF_LD_MIDI	0x07
81 #define W83627HF_LD_GPIO1	0x07
82 #define W83627HF_LD_GPIO5	0x07 /* w83627thf only */
83 #define W83627HF_LD_GPIO2	0x08
84 #define W83627HF_LD_GPIO3	0x09
85 #define W83627HF_LD_GPIO4	0x09 /* w83627thf only */
86 #define W83627HF_LD_ACPI	0x0a
87 #define W83627HF_LD_HWM		0x0b
89 #define DEVID			0x20 /* Register: Device ID */
91 #define W83627THF_GPIO5_EN	0x30 /* w83627thf only */
92 #define W83627THF_GPIO5_IOSR	0xf3 /* w83627thf only */
93 #define W83627THF_GPIO5_DR	0xf4 /* w83627thf only */
95 #define W83687THF_VID_EN	0x29 /* w83687thf only */
96 #define W83687THF_VID_CFG	0xF0 /* w83687thf only */
97 #define W83687THF_VID_DATA	0xF1 /* w83687thf only */
126 	outb(0x87, sio->sioaddr);  in superio_enter()
127 	outb(0x87, sio->sioaddr);  in superio_enter()
129 	return 0;  in superio_enter()
135 	outb(0xAA, sio->sioaddr);  in superio_exit()
139 #define W627_DEVID 0x52
140 #define W627THF_DEVID 0x82
141 #define W697_DEVID 0x60
142 #define W637_DEVID 0x70
143 #define W687THF_DEVID 0x85
144 #define WINB_ACT_REG 0x30
145 #define WINB_BASE_REG 0x60
156 #define W83781D_ADDR_REG_OFFSET 0
161 #define W83781D_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
162 					   (0x554 + (((nr) - 7) * 2)))
163 #define W83781D_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
164 					   (0x555 + (((nr) - 7) * 2)))
165 #define W83781D_REG_IN(nr)     ((nr < 7) ? (0x20 + (nr)) : \
166 					   (0x550 + (nr) - 7))
168 /* nr:0-2 for fans:1-3 */
169 #define W83627HF_REG_FAN_MIN(nr)	(0x3b + (nr))
170 #define W83627HF_REG_FAN(nr)		(0x28 + (nr))
172 #define W83627HF_REG_TEMP2_CONFIG 0x152
173 #define W83627HF_REG_TEMP3_CONFIG 0x252
175 static const u16 w83627hf_reg_temp[]		= { 0x27, 0x150, 0x250 };
176 static const u16 w83627hf_reg_temp_hyst[]	= { 0x3A, 0x153, 0x253 };
177 static const u16 w83627hf_reg_temp_over[]	= { 0x39, 0x155, 0x255 };
179 #define W83781D_REG_BANK 0x4E
181 #define W83781D_REG_CONFIG 0x40
182 #define W83781D_REG_ALARM1 0x459
183 #define W83781D_REG_ALARM2 0x45A
184 #define W83781D_REG_ALARM3 0x45B
186 #define W83781D_REG_BEEP_CONFIG 0x4D
187 #define W83781D_REG_BEEP_INTS1 0x56
188 #define W83781D_REG_BEEP_INTS2 0x57
189 #define W83781D_REG_BEEP_INTS3 0x453
191 #define W83781D_REG_VID_FANDIV 0x47
193 #define W83781D_REG_CHIPID 0x49
194 #define W83781D_REG_WCHIPID 0x58
195 #define W83781D_REG_CHIPMAN 0x4F
196 #define W83781D_REG_PIN 0x4B
198 #define W83781D_REG_VBAT 0x5D
200 #define W83627HF_REG_PWM1 0x5A
201 #define W83627HF_REG_PWM2 0x5B
204 	0x04,		/* FAN 1 mode */
205 	0x04,		/* FAN 2 mode */
206 	0x12,		/* FAN AUX mode */
210 #define W83627THF_REG_PWM1		0x01	/* 697HF/637HF/687THF too */
211 #define W83627THF_REG_PWM2		0x03	/* 697HF/637HF/687THF too */
212 #define W83627THF_REG_PWM3		0x11	/* 637HF/687THF too */
214 #define W83627THF_REG_VRM_OVT_CFG 	0x18	/* 637HF/687THF too */
222 #define W83627HF_REG_PWM_FREQ		0x5C	/* Only for the 627HF */
224 #define W83637HF_REG_PWM_FREQ1		0x00	/* 697HF/687THF too */
225 #define W83637HF_REG_PWM_FREQ2		0x02	/* 697HF/687THF too */
226 #define W83637HF_REG_PWM_FREQ3		0x10	/* 687THF too */
234 #define W83781D_REG_I2C_ADDR 0x48
235 #define W83781D_REG_I2C_SUBADDR 0x4A
238 #define W83781D_REG_SCFG1 0x5D
239 static const u8 BIT_SCFG1[] = { 0x02, 0x04, 0x08 };
240 #define W83781D_REG_SCFG2 0x59
241 static const u8 BIT_SCFG2[] = { 0x10, 0x20, 0x40 };
250 #define IN_TO_REG(val)  (clamp_val((((val) + 8) / 16), 0, 255))
255 	if (rpm == 0)  in FAN_TO_REG()
271 	ntemp += (ntemp < 0 ? -500 : 500);  in TEMP_TO_REG()
280 #define FAN_FROM_REG(val,div) ((val)==0?-1:(val)==255?0:1350000/((val)*(div)))
282 #define PWM_TO_REG(val) (clamp_val((val), 0, 255))
297 	for (i = 0; i < 4; i++) {  in pwm_freq_to_reg_627hf()
308 	unsigned long clock = (reg & 0x80) ? 180000UL : 24000000UL;  in pwm_freq_from_reg()
310 	reg &= 0x7f;  in pwm_freq_from_reg()
312 	if (reg == 0)  in pwm_freq_from_reg()
318 	/* Minimum divider value is 0x01 and maximum is 0x7F */  in pwm_freq_to_reg()
320 		return 0x01;  in pwm_freq_to_reg()
324 		return 0xFF;  in pwm_freq_to_reg()
326 		return 0x80 | (180000UL / (val << 8));  in pwm_freq_to_reg()
329 #define BEEP_MASK_FROM_REG(val)		((val) & 0xff7fff)
330 #define BEEP_MASK_TO_REG(val)		((val) & 0xff7fff)
338 	for (i = 0; i < 7; i++) {  in DIV_TO_REG()
339 		if (val == 0)  in DIV_TO_REG()
392 /* Registers 0x50-0x5f are banked */
395 	if ((reg & 0x00f0) == 0x50) {  in w83627hf_set_bank()
404 	if (reg & 0xff00) {  in w83627hf_reset_bank()
406 		outb_p(0, data->addr + W83781D_DATA_REG_OFFSET);  in w83627hf_reset_bank()
415 	word_sized = (((reg & 0xff00) == 0x100)  in w83627hf_read_value()
416 		   || ((reg & 0xff00) == 0x200))  in w83627hf_read_value()
417 		  && (((reg & 0x00ff) == 0x50)  in w83627hf_read_value()
418 		   || ((reg & 0x00ff) == 0x53)  in w83627hf_read_value()
419 		   || ((reg & 0x00ff) == 0x55));  in w83627hf_read_value()
421 	outb_p(reg & 0xff, data->addr + W83781D_ADDR_REG_OFFSET);  in w83627hf_read_value()
424 		outb_p((reg & 0xff) + 1,  in w83627hf_read_value()
440 	word_sized = (((reg & 0xff00) == 0x100)  in w83627hf_write_value()
441 		   || ((reg & 0xff00) == 0x200))  in w83627hf_write_value()
442 		  && (((reg & 0x00ff) == 0x53)  in w83627hf_write_value()
443 		   || ((reg & 0x00ff) == 0x55));  in w83627hf_write_value()
445 	outb_p(reg & 0xff, data->addr + W83781D_ADDR_REG_OFFSET);  in w83627hf_write_value()
449 		outb_p((reg & 0xff) + 1,  in w83627hf_write_value()
452 	outb_p(value & 0xff,  in w83627hf_write_value()
456 	return 0;  in w83627hf_write_value()
464 	data->fan_div[0] = (reg >> 4) & 0x03;  in w83627hf_update_fan_div()
465 	data->fan_div[1] = (reg >> 6) & 0x03;  in w83627hf_update_fan_div()
468 				       W83781D_REG_PIN) >> 6) & 0x03;  in w83627hf_update_fan_div()
471 	data->fan_div[0] |= (reg >> 3) & 0x04;  in w83627hf_update_fan_div()
472 	data->fan_div[1] |= (reg >> 4) & 0x04;  in w83627hf_update_fan_div()
474 		data->fan_div[2] |= (reg >> 5) & 0x04;  in w83627hf_update_fan_div()
487 		for (i = 0; i <= 8; i++) {  in w83627hf_update_device()
502 		for (i = 0; i <= 2; i++) {  in w83627hf_update_device()
509 		for (i = 0; i <= 2; i++) {  in w83627hf_update_device()
512 			/* bits 0-3 are reserved  in 627THF */  in w83627hf_update_device()
514 				tmp &= 0xf0;  in w83627hf_update_device()
523 				data->pwm_freq[0] = tmp & 0x07;  in w83627hf_update_device()
524 				data->pwm_freq[1] = (tmp >> 4) & 0x07;  in w83627hf_update_device()
535 			for (i = 0; i < num_pwms; i++) {  in w83627hf_update_device()
540 					& 0x03) + 1;  in w83627hf_update_device()
543 		for (i = 0; i < num_temps; i++) {  in w83627hf_update_device()
581 	return 0;  in w83627hf_suspend()
591 	for (i = 0; i <= 8; i++) {  in w83627hf_resume()
602 	for (i = 0; i <= 2; i++)  in w83627hf_resume()
605 	for (i = 0; i < num_temps; i++) {  in w83627hf_resume()
624 	return 0;  in w83627hf_resume()
640 	int res = 0xff, sel;  in w83627thf_read_gpio5()
655 	res = 0xff;  in w83627thf_read_gpio5()
667 	sel = superio_inb(sio_data, W83627THF_GPIO5_IOSR) & 0x3f;  in w83627thf_read_gpio5()
668 	if ((sel & 0x1f) != 0x1f) {  in w83627thf_read_gpio5()
685 	int res = 0xff;  in w83687thf_read_vid()
713 	res = superio_inb(sio_data, W83687THF_VID_DATA) & 0x3f;  in w83687thf_read_vid()
731 		w83627hf_write_value(data, W83781D_REG_I2C_SUBADDR, 0x89);  in w83627hf_init_device()
739 		data->vid = (lo & 0x0f) | ((hi & 0x01) << 4);  in w83627hf_init_device()
771 		if (tmp & 0x01) {  in w83627hf_init_device()
775 				tmp & 0xfe);  in w83627hf_init_device()
782 			if (tmp & 0x01) {  in w83627hf_init_device()
786 					W83627HF_REG_TEMP3_CONFIG, tmp & 0xfe);  in w83627hf_init_device()
794 						W83781D_REG_CONFIG) & 0xf7)  in w83627hf_init_device()
795 			    | 0x01);  in w83627hf_init_device()
799 	if (!(tmp & 0x01))  in w83627hf_init_device()
800 		w83627hf_write_value(data, W83781D_REG_VBAT, tmp | 0x01);  in w83627hf_init_device()
808 	if ((data->vrm_ovt & 0x01) &&  in show_in_0()
825 	return show_in_0(data, buf, data->in[0]);  in in0_input_show()
833 	return show_in_0(data, buf, data->in_min[0]);  in in0_min_show()
850 	if ((data->vrm_ovt & 0x01) &&  in in0_min_store()
855 		data->in_min[0] =  in in0_min_store()
856 			clamp_val(((val * 100) - 70000 + 244) / 488, 0, 255);  in in0_min_store()
859 		data->in_min[0] = IN_TO_REG(val);  in in0_min_store()
861 	w83627hf_write_value(data, W83781D_REG_IN_MIN(0), data->in_min[0]);  in in0_min_store()
872 	return show_in_0(data, buf, data->in_max[0]);  in in0_max_show()
889 	if ((data->vrm_ovt & 0x01) &&  in in0_max_store()
894 		data->in_max[0] =  in in0_max_store()
895 			clamp_val(((val * 100) - 70000 + 244) / 488, 0, 255);  in in0_max_store()
898 		data->in_max[0] = IN_TO_REG(val);  in in0_max_store()
900 	w83627hf_write_value(data, W83781D_REG_IN_MAX(0), data->in_max[0]);  in in0_max_store()
915 static SENSOR_DEVICE_ATTR_RO(in0_alarm, alarm, 0);
989 static SENSOR_DEVICE_ATTR_RW(in0_beep, beep, 0);
1136 static SENSOR_DEVICE_ATTR_RO(fan1_input, fan_input, 0);
1137 static SENSOR_DEVICE_ATTR_RW(fan1_min, fan_min, 0);
1182 	       & (nr==0 ? 0xcf : 0x3f))  in fan_div_store()
1183 	    | ((data->fan_div[nr] & 0x03) << (nr==0 ? 4 : 6));  in fan_div_store()
1188 	    | ((data->fan_div[nr] & 0x04) << (3 + nr));  in fan_div_store()
1199 static SENSOR_DEVICE_ATTR_RW(fan1_div, fan_div, 0);
1281 static SENSOR_DEVICE_ATTR_RO(temp1_input, temp, 0);
1282 static SENSOR_DEVICE_ATTR_RW(temp1_max, temp_max, 0);
1283 static SENSOR_DEVICE_ATTR_RW(temp1_max_hyst, temp_max_hyst, 0);
1356 static SENSOR_DEVICE_ATTR_RW(temp1_type, temp_type, 0);
1413 	data->beep_mask = (data->beep_mask & 0x8000)  in beep_mask_store()
1416 			    data->beep_mask & 0xff);  in beep_mask_store()
1418 			    ((data->beep_mask) >> 16) & 0xff);  in beep_mask_store()
1420 			    (data->beep_mask >> 8) & 0xff);  in beep_mask_store()
1452 		/* bits 0-3 are reserved  in 627THF */  in pwm_store()
1453 		data->pwm[nr] = PWM_TO_REG(val) & 0xf0;  in pwm_store()
1458 				     W836X7HF_REG_PWM(data->type, nr)) & 0x0f));  in pwm_store()
1470 static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0);
1535 	static const u8 mask[]={0xF8, 0x8F};  in pwm_freq_store()
1561 static SENSOR_DEVICE_ATTR_RW(pwm1_freq, pwm_freq, 0);
1630 	reg &= ~(0x03 << W83627THF_PWM_ENABLE_SHIFT[nr]);  in pwm_enable_store()
1637 static SENSOR_DEVICE_ATTR_RW(pwm1_enable, pwm_enable, 0);
1681 	res = platform_get_resource(pdev, IORESOURCE_IO, 0);  in w83627hf_probe()
1683 		dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",  in w83627hf_probe()
1704 	for (i = 0; i <= 2; i++)  in w83627hf_probe()
1777 	if (data->type != w83697hf && data->vid != 0xff) {  in w83627hf_probe()
1823 	return 0;  in w83627hf_probe()
1887 	case 0xff:	/* No device at all */  in w83627hf_find()
1890 		pr_debug(DRVNAME ": Unsupported chip (DEVID=0x%02x)\n", val);  in w83627hf_find()
1898 	if (*addr == 0) {  in w83627hf_find()
1904 	if (!(val & 0x01)) {  in w83627hf_find()
1906 		superio_outb(sio_data, WINB_ACT_REG, val | 0x01);  in w83627hf_find()
1909 	err = 0;  in w83627hf_find()
1959 	return 0;  in w83627hf_device_add()
1973 	if (w83627hf_find(0x2e, &address, &sio_data)  in sensors_w83627hf_init()
1974 	 && w83627hf_find(0x4e, &address, &sio_data))  in sensors_w83627hf_init()
1986 	return 0;  in sensors_w83627hf_init()