Lines Matching +full:fpga +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
10 #include <linux/mfd/intel-m10-bmc.h>
40 { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Die Temperature" },
52 { 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage" },
61 { 0x140, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Current" },
104 { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Core Temperature" },
106 { 0x12c, 0x130, 0x134, 0x0, 0x0, 500, "FPGA Transceiver Temperature" },
125 { 0x198, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage" },
136 { 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Current" },
233 { 0x108, 0x0, 0x10c, 0x0, 0x0, 1000, "FPGA 1 Temperature" },
234 { 0x110, 0x0, 0x114, 0x0, 0x0, 1000, "FPGA 2 Temperature" },
237 { 0x128, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 1.2V Temperature" },
238 { 0x134, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 5V Temperature" },
239 { 0x140, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.9V Temperature" },
240 { 0x14c, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.85V Temperature" },
243 { 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" },
244 { 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" },
245 { 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" },
246 { 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" },
252 { 0x120, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Voltage" },
253 { 0x12c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Voltage" },
254 { 0x138, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Voltage" },
255 { 0x144, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Voltage" },
259 { 0x17c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Voltage" },
268 { 0x124, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Current" },
269 { 0x130, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Current" },
270 { 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Current" },
271 { 0x148, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Current" },
275 { 0x178, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Current" },
344 { 0x444, 0x448, 0x44c, 0x0, 0x0, 500, "FPGA E-TILE Temperature #1" },
345 { 0x450, 0x454, 0x458, 0x0, 0x0, 500, "FPGA E-TILE Temperature #2" },
346 { 0x45c, 0x460, 0x464, 0x0, 0x0, 500, "FPGA E-TILE Temperature #3" },
347 { 0x468, 0x46c, 0x470, 0x0, 0x0, 500, "FPGA E-TILE Temperature #4" },
348 { 0x474, 0x478, 0x47c, 0x0, 0x0, 500, "FPGA P-TILE Temperature" },
349 { 0x484, 0x488, 0x48c, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #1" },
350 { 0x490, 0x494, 0x498, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #2" },
351 { 0x49c, 0x4a0, 0x4a4, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #3" },
352 { 0x4a8, 0x4ac, 0x4b0, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #4" },
353 { 0x4b4, 0x4b8, 0x4bc, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #5" },
354 { 0x4c0, 0x4c4, 0x4c8, 0x0, 0x0, 500, "FPGA FABRIC Remote Digital Temperature #1" },
355 { 0x4cc, 0x4d0, 0x4d4, 0x0, 0x0, 500, "FPGA FABRIC Remote Digital Temperature #2" },
356 { 0x4d8, 0x4dc, 0x4e0, 0x0, 0x0, 500, "FPGA FABRIC Remote Digital Temperature #3" },
357 { 0x4e4, 0x4e8, 0x4ec, 0x0, 0x0, 500, "FPGA FABRIC Remote Digital Temperature #4" },
358 { 0x4f0, 0x4f4, 0x4f8, 0x52c, 0x0, 500, "Board Top Near FPGA Temperature" },
366 { 0x554, 0x0, 0x0, 0x0, 0x0, 500, "FPGA Core Voltage Phase 0 VR Temperature" },
367 { 0x560, 0x0, 0x0, 0x0, 0x0, 500, "FPGA Core Voltage Phase 1 VR Temperature" },
368 { 0x56c, 0x0, 0x0, 0x0, 0x0, 500, "FPGA Core Voltage Phase 2 VR Temperature" },
369 { 0x578, 0x0, 0x0, 0x0, 0x0, 500, "FPGA Core Voltage VR Controller Temperature" },
370 { 0x584, 0x0, 0x0, 0x0, 0x0, 500, "FPGA VCCH VR Temperature" },
371 { 0x590, 0x0, 0x0, 0x0, 0x0, 500, "FPGA VCC_1V2 VR Temperature" },
372 { 0x59c, 0x0, 0x0, 0x0, 0x0, 500, "FPGA VCCH, VCC_1V2 VR Controller Temperature" },
375 { 0x5c4, 0x5c8, 0x5cc, 0x5c0, 0x0, 500, "FPGA P-Tile Temperature [Remote]" },
376 { 0x5d0, 0x5d4, 0x5d8, 0x5c0, 0x0, 500, "FPGA E-Tile Temperature [Remote]" },
377 { 0x5dc, 0x5e0, 0x5e4, 0x5c0, 0x0, 500, "FPGA SDM Temperature [Remote]" },
378 { 0x5e8, 0x5ec, 0x5f0, 0x5c0, 0x0, 500, "FPGA Corner Temperature [Remote]" },
385 { 0x63c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage Rail Voltage" },
386 { 0x644, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCCH Rail Voltage" },
387 { 0x64c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCC_1V2 Rail Voltage" },
388 { 0x654, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCCH_GXER_1V1, VCCA_1V8 Voltage" },
389 { 0x664, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCCIO_1V2 Voltage" },
419 { 0x640, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage Rail Current" },
420 { 0x648, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCCH Rail Current" },
421 { 0x650, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCC_1V2 Rail Current" },
422 { 0x658, 0x65c, 0x660, 0x0, 0x0, 1, "FPGA VCCH_GXER_1V1, VCCA_1V8 Current" },
423 { 0x668, 0x66c, 0x670, 0x0, 0x0, 1, "FPGA VCCIO_1V2 Current" },
581 tbl = hw->bdata->tables[type]; in find_sensor_data()
583 return ERR_PTR(-EOPNOTSUPP); in find_sensor_data()
595 ret = m10bmc_sys_read(hw->m10bmc, regoff, ®val); in do_sensor_read()
607 return -ENODATA; in do_sensor_read()
609 *val = regval * data->multiplier; in do_sensor_read()
631 reg = data->reg_input; in m10bmc_hwmon_read()
634 reg_hyst = data->reg_hyst; in m10bmc_hwmon_read()
637 reg = data->reg_max; in m10bmc_hwmon_read()
640 reg_hyst = data->reg_hyst; in m10bmc_hwmon_read()
643 reg = data->reg_crit; in m10bmc_hwmon_read()
646 return -EOPNOTSUPP; in m10bmc_hwmon_read()
652 reg = data->reg_input; in m10bmc_hwmon_read()
655 reg = data->reg_max; in m10bmc_hwmon_read()
658 reg = data->reg_crit; in m10bmc_hwmon_read()
661 reg = data->reg_min; in m10bmc_hwmon_read()
664 return -EOPNOTSUPP; in m10bmc_hwmon_read()
670 reg = data->reg_input; in m10bmc_hwmon_read()
673 reg = data->reg_max; in m10bmc_hwmon_read()
676 reg = data->reg_crit; in m10bmc_hwmon_read()
679 return -EOPNOTSUPP; in m10bmc_hwmon_read()
685 reg = data->reg_input; in m10bmc_hwmon_read()
688 return -EOPNOTSUPP; in m10bmc_hwmon_read()
692 return -EOPNOTSUPP; in m10bmc_hwmon_read()
696 return -EOPNOTSUPP; in m10bmc_hwmon_read()
707 value -= hyst; in m10bmc_hwmon_read()
726 *str = data->label; in m10bmc_hwmon_read_string()
740 struct intel_m10bmc *m10bmc = dev_get_drvdata(pdev->dev.parent); in m10bmc_hwmon_probe()
741 struct device *hwmon_dev, *dev = &pdev->dev; in m10bmc_hwmon_probe()
746 return -ENOMEM; in m10bmc_hwmon_probe()
748 hw->dev = dev; in m10bmc_hwmon_probe()
749 hw->m10bmc = m10bmc; in m10bmc_hwmon_probe()
750 hw->bdata = (const struct m10bmc_hwmon_board_data *)id->driver_data; in m10bmc_hwmon_probe()
752 hw->chip.info = hw->bdata->hinfo; in m10bmc_hwmon_probe()
753 hw->chip.ops = &m10bmc_hwmon_ops; in m10bmc_hwmon_probe()
755 hw->hw_name = devm_hwmon_sanitize_name(dev, id->name); in m10bmc_hwmon_probe()
756 if (IS_ERR(hw->hw_name)) in m10bmc_hwmon_probe()
757 return PTR_ERR(hw->hw_name); in m10bmc_hwmon_probe()
759 hwmon_dev = devm_hwmon_device_register_with_info(dev, hw->hw_name, in m10bmc_hwmon_probe()
760 hw, &hw->chip, NULL); in m10bmc_hwmon_probe()
766 .name = "n3000bmc-hwmon",
770 .name = "d5005bmc-hwmon",
774 .name = "n5010bmc-hwmon",
778 .name = "n6000bmc-hwmon",
787 .name = "intel-m10-bmc-hwmon",