18 #define DC_MAP_CONF_PTR(n)	(0x108 + ((n) & ~0x1) * 2)
19 #define DC_MAP_CONF_VAL(n)	(0x144 + ((n) & ~0x1) * 2)
21 #define DC_EVT_NF		0
31 #define DC_EVT_NEW_ADDR_W_0	0
44 #define DC_WR_CH_CONF		0x0
45 #define DC_WR_CH_ADDR		0x4
46 #define DC_RL_CH(evt)		(8 + ((evt) & ~0x1) * 2)
48 #define DC_GEN			0xd4
49 #define DC_DISP_CONF1(disp)	(0xd8 + (disp) * 4)
50 #define DC_DISP_CONF2(disp)	(0xe8 + (disp) * 4)
51 #define DC_STAT			0x1c8
53 #define WROD(lf)		(0x18 | ((lf) << 1))
54 #define WRG			0x01
55 #define WCLK			0xc9
57 #define SYNC_WAVE 0
63 #define DC_WR_CH_CONF_WORD_SIZE_8		(0 << 0)
64 #define DC_WR_CH_CONF_WORD_SIZE_16		(1 << 0)
65 #define DC_WR_CH_CONF_WORD_SIZE_24		(2 << 0)
66 #define DC_WR_CH_CONF_WORD_SIZE_32		(3 << 0)
67 #define DC_WR_CH_CONF_DISP_ID_PARALLEL(i)	(((i) & 0x1) << 3)
74 #define DC_WR_CH_CONF_PROG_DISP_ID(i)		(((i) & 0x1) << 3)
114 	reg &= ~(0xffff << (16 * (event & 0x1)));  in dc_link_event()
115 	reg |= ((addr << 8) | priority) << (16 * (event & 0x1));  in dc_link_event()
126 		reg1 = (operand << 20) & 0xfff00000;  in dc_write_tmpl()
129 		reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);  in dc_write_tmpl()
132 		reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);  in dc_write_tmpl()
165 	u32 reg = 0;  in ipu_dc_init_sync()
189 		addr = 0;  in ipu_dc_init_sync()
197 		dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);  in ipu_dc_init_sync()
204 		dc_write_tmpl(dc, addr + 2, WROD(0), 0, map, SYNC_WAVE, 8, sync, 1);  in ipu_dc_init_sync()
205 		dc_write_tmpl(dc, addr + 3, WROD(0), 0, map, SYNC_WAVE, 4, sync, 0);  in ipu_dc_init_sync()
206 		dc_write_tmpl(dc, addr + 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);  in ipu_dc_init_sync()
207 		dc_write_tmpl(dc, addr + 1, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);  in ipu_dc_init_sync()
210 	dc_link_event(dc, DC_EVT_NF, 0, 0);  in ipu_dc_init_sync()
211 	dc_link_event(dc, DC_EVT_NFIELD, 0, 0);  in ipu_dc_init_sync()
212 	dc_link_event(dc, DC_EVT_EOF, 0, 0);  in ipu_dc_init_sync()
213 	dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);  in ipu_dc_init_sync()
214 	dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);  in ipu_dc_init_sync()
215 	dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);  in ipu_dc_init_sync()
224 	writel(0x0, dc->base + DC_WR_CH_ADDR);  in ipu_dc_init_sync()
227 	return 0;  in ipu_dc_init_sync()
276 	if (priv->use_count < 0)  in ipu_dc_disable()
277 		priv->use_count = 0;  in ipu_dc_disable()
290 	reg &= ~(0xffff << (16 * (ptr & 0x1)));  in ipu_dc_map_config()
291 	reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));  in ipu_dc_map_config()
295 	reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));  in ipu_dc_map_config()
296 	reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));  in ipu_dc_map_config()
304 	writel(reg & ~(0xffff << (16 * (map & 0x1))),  in ipu_dc_map_clear()
348 		0, 0x1c, 0x38, 0x54, 0x58, 0x5c, 0x78, 0, 0x94, 0xb4  in ipu_dc_init()
365 	for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {  in ipu_dc_init()
374 	writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),  in ipu_dc_init()
382 	dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",  in ipu_dc_init()
387 	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */  in ipu_dc_init()
388 	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */  in ipu_dc_init()
389 	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */  in ipu_dc_init()
393 	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */  in ipu_dc_init()
394 	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */  in ipu_dc_init()
395 	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */  in ipu_dc_init()
399 	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */  in ipu_dc_init()
400 	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */  in ipu_dc_init()
401 	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */  in ipu_dc_init()
405 	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */  in ipu_dc_init()
406 	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */  in ipu_dc_init()
407 	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */  in ipu_dc_init()
411 	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */  in ipu_dc_init()
412 	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */  in ipu_dc_init()
413 	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */  in ipu_dc_init()
417 	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */  in ipu_dc_init()
418 	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */  in ipu_dc_init()
419 	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */  in ipu_dc_init()
421 	return 0;  in ipu_dc_init()