250 #define idma_mask(ch)			(1 << ((ch) & 0x1f))  macro
268 	ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));  in __ipu_idmac_reset_current_buffer()
282 		reg |= idma_mask(channel->num);  in ipu_idmac_set_double_buffer()
284 		reg &= ~idma_mask(channel->num);  in ipu_idmac_set_double_buffer()
427 	return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;  in ipu_idmac_get_current_buffer()
451 	return ((reg & idma_mask(channel->num)) != 0);  in ipu_idmac_buffer_is_ready()
465 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));  in ipu_idmac_select_buffer()
467 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));  in ipu_idmac_select_buffer()
484 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));  in ipu_idmac_clear_buffer()
487 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));  in ipu_idmac_clear_buffer()
490 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));  in ipu_idmac_clear_buffer()
510 	val |= idma_mask(channel->num);  in ipu_idmac_enable_channel()
521 	return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));  in ipu_idmac_channel_busy()
532 			idma_mask(channel->num)) {  in ipu_idmac_wait_busy()
552 	val &= ~idma_mask(channel->num);  in ipu_idmac_disable_channel()
561 			idma_mask(channel->num)) {  in ipu_idmac_disable_channel()
562 		ipu_cm_write(ipu, idma_mask(channel->num),  in ipu_idmac_disable_channel()
567 			idma_mask(channel->num)) {  in ipu_idmac_disable_channel()
568 		ipu_cm_write(ipu, idma_mask(channel->num),  in ipu_idmac_disable_channel()
576 	val &= ~idma_mask(channel->num);  in ipu_idmac_disable_channel()