Lines Matching +full:host1x +full:- +full:class

1 // SPDX-License-Identifier: GPL-2.0-only
6  * Copyright (C) 2011-2017 NVIDIA Corporation
14 static void host1x_debug_show_channel_cdma(struct host1x *host,  in host1x_debug_show_channel_cdma()
18 	struct host1x_cdma *cdma = &ch->cdma;  in host1x_debug_show_channel_cdma()
21 	u32 offset, class;  in host1x_debug_show_channel_cdma()  local
40 	class = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_CLASS);  in host1x_debug_show_channel_cdma()
43 	host1x_debug_output(o, "%u-%s: ", ch->id, dev_name(ch->dev));  in host1x_debug_show_channel_cdma()
46 	    !ch->cdma.push_buffer.mapped) {  in host1x_debug_show_channel_cdma()
51 	if (class == HOST1X_CLASS_HOST1X && offset == HOST1X_UCLASS_WAIT_SYNCPT)  in host1x_debug_show_channel_cdma()
54 		host1x_debug_output(o, "active class %02x, offset %04x\n",  in host1x_debug_show_channel_cdma()
55 				    class, offset);  in host1x_debug_show_channel_cdma()
66 static void host1x_debug_show_channel_fifo(struct host1x *host,  in host1x_debug_show_channel_fifo()
77 	host1x_debug_output(o, "%u: fifo:\n", ch->id);  in host1x_debug_show_channel_fifo()
95 	val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);  in host1x_debug_show_channel_fifo()
102 	val = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_SETUP(ch->id));  in host1x_debug_show_channel_fifo()
109 		val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);  in host1x_debug_show_channel_fifo()
119 					    rd_ptr - start, val);  in host1x_debug_show_channel_fifo()
124 			data_count--;  in host1x_debug_show_channel_fifo()
142 static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)  in host1x_debug_show_mlocks()