20  * DOC: Multi-tile Design
22  * Different vendors use the term "tile" a bit differently, but in the Intel
23  * world, a 'tile' is pretty close to what most people would think of as being
25  * that's what is referred to as a "multi-tile device."  In such cases, pretty
26  * much all hardware is replicated per-tile, although certain responsibilities
28  * solely by the "root tile."  A multi-tile platform takes care of tying the
30  * are forwarded to the root tile, the per-tile vram is combined into a single
34  * the subset of a GPU/tile that is responsible for implementing graphics
39  * Historically most Intel devices were single-tile devices that contained a
40  * single GT.  PVC is an example of an Intel platform built on a multi-tile
41  * design (i.e., multiple GPUs behind a single PCI device); each PVC tile only
47  * differently than multi-tile platforms like PVC where nearly everything is
50  * Per-tile functionality (shared by all GTs within the tile):
66  *    within the complete MMIO space provided by the tile, but at different
77  * xe_tile_alloc - Perform per-tile memory allocation
78  * @tile: Tile to perform allocations for
80  * Allocates various per-tile data structures using DRM-managed allocations.
85 static int xe_tile_alloc(struct xe_tile *tile)  in xe_tile_alloc()  argument
87 	struct drm_device *drm = &tile_to_xe(tile)->drm;  in xe_tile_alloc()
89 	tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt),  in xe_tile_alloc()
91 	if (!tile->mem.ggtt)  in xe_tile_alloc()
93 	tile->mem.ggtt->tile = tile;  in xe_tile_alloc()
95 	tile->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*tile->mem.vram_mgr), GFP_KERNEL);  in xe_tile_alloc()
96 	if (!tile->mem.vram_mgr)  in xe_tile_alloc()
103  * xe_tile_init_early - Initialize the tile and primary GT
104  * @tile: Tile to initialize
106  * @id: Tile ID
108  * Initializes per-tile resources that don't require any interactions with the
113 int xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id)  in xe_tile_init_early()  argument
117 	tile->xe = xe;  in xe_tile_init_early()
118 	tile->id = id;  in xe_tile_init_early()
120 	err = xe_tile_alloc(tile);  in xe_tile_init_early()
124 	tile->primary_gt = xe_gt_alloc(tile);  in xe_tile_init_early()
125 	if (IS_ERR(tile->primary_gt))  in xe_tile_init_early()
126 		return PTR_ERR(tile->primary_gt);  in xe_tile_init_early()
128 	xe_pcode_init(tile);  in xe_tile_init_early()
133 static int tile_ttm_mgr_init(struct xe_tile *tile)  in tile_ttm_mgr_init()  argument
135 	struct xe_device *xe = tile_to_xe(tile);  in tile_ttm_mgr_init()
138 	if (tile->mem.vram.usable_size) {  in tile_ttm_mgr_init()
139 		err = xe_ttm_vram_mgr_init(tile, tile->mem.vram_mgr);  in tile_ttm_mgr_init()
142 		xe->info.mem_region_mask |= BIT(tile->id) << 1;  in tile_ttm_mgr_init()
149  * xe_tile_init_noalloc - Init tile up to the point where allocations can happen.
150  * @tile: The tile to initialize.
152  * This function prepares the tile to allow memory allocations to VRAM, but is
157  * Note that since this is tile initialization, it should not perform any
162 int xe_tile_init_noalloc(struct xe_tile *tile)  in xe_tile_init_noalloc()  argument
166 	err = tile_ttm_mgr_init(tile);  in xe_tile_init_noalloc()
170 	tile->mem.kernel_bb_pool = xe_sa_bo_manager_init(tile, SZ_1M, 16);  in xe_tile_init_noalloc()
171 	if (IS_ERR(tile->mem.kernel_bb_pool))  in xe_tile_init_noalloc()
172 		return PTR_ERR(tile->mem.kernel_bb_pool);  in xe_tile_init_noalloc()
174 	xe_wa_apply_tile_workarounds(tile);  in xe_tile_init_noalloc()
176 	err = xe_tile_sysfs_init(tile);  in xe_tile_init_noalloc()
181 void xe_tile_migrate_wait(struct xe_tile *tile)  in xe_tile_migrate_wait()  argument
183 	xe_migrate_wait(tile->migrate);  in xe_tile_migrate_wait()