31 #define LRC_VALID				BIT_ULL(0)
110  * [5:0]: Number of NOPs or registers to set values to in case of
115  * is used for offsets smaller than 0x200 while the latter is for values bigger
120  * [6:0]: Register offset, without considering the engine base.
131 #define POSTED BIT(0)  in set_offsets()
132 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))  in set_offsets()
134 	(((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \  in set_offsets()
135 	(((x) >> 2) & 0x7f)  in set_offsets()
148 		count = *data & 0x3f;  in set_offsets()
160 			u32 offset = 0;  in set_offsets()
169 			regs[0] = base + (offset << 2);  in set_offsets()
174 	*regs = MI_BATCH_BUFFER_END | BIT(0);  in set_offsets()
180 	REG16(0x244),
181 	REG(0x034),
182 	REG(0x030),
183 	REG(0x038),
184 	REG(0x03c),
185 	REG(0x168),
186 	REG(0x140),
187 	REG(0x110),
188 	REG(0x1c0),
189 	REG(0x1c4),
190 	REG(0x1c8),
191 	REG(0x180),
192 	REG16(0x2b4),
196 	REG16(0x3a8),
197 	REG16(0x28c),
198 	REG16(0x288),
199 	REG16(0x284),
200 	REG16(0x280),
201 	REG16(0x27c),
202 	REG16(0x278),
203 	REG16(0x274),
204 	REG16(0x270),
206 	0
212 	REG16(0x244),
213 	REG(0x034),
214 	REG(0x030),
215 	REG(0x038),
216 	REG(0x03c),
217 	REG(0x168),
218 	REG(0x140),
219 	REG(0x110),
220 	REG(0x1c0),
221 	REG(0x1c4),
222 	REG(0x1c8),
223 	REG(0x180),
224 	REG16(0x2b4),
225 	REG(0x120),
226 	REG(0x124),
230 	REG16(0x3a8),
231 	REG16(0x28c),
232 	REG16(0x288),
233 	REG16(0x284),
234 	REG16(0x280),
235 	REG16(0x27c),
236 	REG16(0x278),
237 	REG16(0x274),
238 	REG16(0x270),
240 	0
246 	REG16(0x244),
247 	REG(0x034),
248 	REG(0x030),
249 	REG(0x038),
250 	REG(0x03c),
251 	REG(0x168),
252 	REG(0x140),
253 	REG(0x110),
254 	REG(0x1c0),
255 	REG(0x1c4),
256 	REG(0x1c8),
257 	REG(0x180),
258 	REG16(0x2b4),
262 	REG16(0x3a8),
263 	REG16(0x28c),
264 	REG16(0x288),
265 	REG16(0x284),
266 	REG16(0x280),
267 	REG16(0x27c),
268 	REG16(0x278),
269 	REG16(0x274),
270 	REG16(0x270),
273 	REG(0x1b0),
274 	REG16(0x5a8),
275 	REG16(0x5ac),
278 	LRI(1, 0),
279 	REG(0x0c8),
283 	REG16(0x588),
284 	REG16(0x588),
285 	REG16(0x588),
286 	REG16(0x588),
287 	REG16(0x588),
288 	REG16(0x588),
289 	REG(0x028),
290 	REG(0x09c),
291 	REG(0x0c0),
292 	REG(0x178),
293 	REG(0x17c),
294 	REG16(0x358),
295 	REG(0x170),
296 	REG(0x150),
297 	REG(0x154),
298 	REG(0x158),
299 	REG16(0x41c),
300 	REG16(0x600),
301 	REG16(0x604),
302 	REG16(0x608),
303 	REG16(0x60c),
304 	REG16(0x610),
305 	REG16(0x614),
306 	REG16(0x618),
307 	REG16(0x61c),
308 	REG16(0x620),
309 	REG16(0x624),
310 	REG16(0x628),
311 	REG16(0x62c),
312 	REG16(0x630),
313 	REG16(0x634),
314 	REG16(0x638),
315 	REG16(0x63c),
316 	REG16(0x640),
317 	REG16(0x644),
318 	REG16(0x648),
319 	REG16(0x64c),
320 	REG16(0x650),
321 	REG16(0x654),
322 	REG16(0x658),
323 	REG16(0x65c),
324 	REG16(0x660),
325 	REG16(0x664),
326 	REG16(0x668),
327 	REG16(0x66c),
328 	REG16(0x670),
329 	REG16(0x674),
330 	REG16(0x678),
331 	REG16(0x67c),
332 	REG(0x068),
333 	REG(0x084),
336 	0
342 	REG16(0x244),
343 	REG(0x034),
344 	REG(0x030),
345 	REG(0x038),
346 	REG(0x03c),
347 	REG(0x168),
348 	REG(0x140),
349 	REG(0x110),
350 	REG(0x1c0),
351 	REG(0x1c4),
352 	REG(0x1c8),
353 	REG(0x180),
354 	REG16(0x2b4),
358 	REG16(0x3a8),
359 	REG16(0x28c),
360 	REG16(0x288),
361 	REG16(0x284),
362 	REG16(0x280),
363 	REG16(0x27c),
364 	REG16(0x278),
365 	REG16(0x274),
366 	REG16(0x270),
369 	REG(0x1b0),
370 	REG16(0x5a8),
371 	REG16(0x5ac),
374 	LRI(1, 0),
375 	REG(0x0c8),
377 	0
383 	REG16(0x244),
384 	REG(0x034),
385 	REG(0x030),
386 	REG(0x038),
387 	REG(0x03c),
388 	REG(0x168),
389 	REG(0x140),
390 	REG(0x110),
391 	REG(0x1c0),
392 	REG(0x1c4),
393 	REG(0x1c8),
394 	REG(0x180),
395 	REG16(0x2b4),
396 	REG(0x120),
397 	REG(0x124),
401 	REG16(0x3a8),
402 	REG16(0x28c),
403 	REG16(0x288),
404 	REG16(0x284),
405 	REG16(0x280),
406 	REG16(0x27c),
407 	REG16(0x278),
408 	REG16(0x274),
409 	REG16(0x270),
412 	REG(0x1b0),
413 	REG16(0x5a8),
414 	REG16(0x5ac),
417 	LRI(1, 0),
418 	REG(0x0c8),
420 	0
426 	REG16(0x244),
427 	REG(0x034),
428 	REG(0x030),
429 	REG(0x038),
430 	REG(0x03c),
431 	REG(0x168),
432 	REG(0x140),
433 	REG(0x110),
434 	REG(0x1c0),
435 	REG(0x1c4),
436 	REG(0x1c8),
437 	REG(0x180),
438 	REG16(0x2b4),
439 	REG(0x120),
440 	REG(0x124),
444 	REG16(0x3a8),
445 	REG16(0x28c),
446 	REG16(0x288),
447 	REG16(0x284),
448 	REG16(0x280),
449 	REG16(0x27c),
450 	REG16(0x278),
451 	REG16(0x274),
452 	REG16(0x270),
456 	REG16(0x5a8),
457 	REG16(0x5ac),
460 	LRI(1, 0),
461 	REG(0x0c8),
463 	0
467 	NOP(1),                 /* [0x00] */ \
468 	LRI(15, POSTED),        /* [0x01] */ \
469 	REG16(0x244),           /* [0x02] CTXT_SR_CTL */ \
470 	REG(0x034),             /* [0x04] RING_BUFFER_HEAD */ \
471 	REG(0x030),             /* [0x06] RING_BUFFER_TAIL */ \
472 	REG(0x038),             /* [0x08] RING_BUFFER_START */ \
473 	REG(0x03c),             /* [0x0a] RING_BUFFER_CONTROL */ \
474 	REG(0x168),             /* [0x0c] BB_ADDR_UDW */ \
475 	REG(0x140),             /* [0x0e] BB_ADDR */ \
476 	REG(0x110),             /* [0x10] BB_STATE */ \
477 	REG(0x1c0),             /* [0x12] BB_PER_CTX_PTR */ \
478 	REG(0x1c4),             /* [0x14] RCS_INDIRECT_CTX */ \
479 	REG(0x1c8),             /* [0x16] RCS_INDIRECT_CTX_OFFSET */ \
480 	REG(0x180),             /* [0x18] CCID */ \
481 	REG16(0x2b4),           /* [0x1a] SEMAPHORE_TOKEN */ \
482 	REG(0x120),             /* [0x1c] PRT_BB_STATE */ \
483 	REG(0x124),             /* [0x1e] PRT_BB_STATE_UDW */ \
485 	NOP(1),                 /* [0x20] */ \
486 	LRI(9, POSTED),         /* [0x21] */ \
487 	REG16(0x3a8),           /* [0x22] CTX_TIMESTAMP */ \
488 	REG16(0x3ac),           /* [0x24] CTX_TIMESTAMP_UDW */ \
489 	REG(0x108),             /* [0x26] INDIRECT_RING_STATE */ \
490 	REG16(0x284),           /* [0x28] dummy reg */ \
491 	REG16(0x280),           /* [0x2a] CS_ACC_CTR_THOLD */ \
492 	REG16(0x27c),           /* [0x2c] CS_CTX_SYS_PASID */ \
493 	REG16(0x278),           /* [0x2e] CS_CTX_ASID */ \
494 	REG16(0x274),           /* [0x30] PTBP_UDW */ \
495 	REG16(0x270)            /* [0x32] PTBP_LDW */
500 	NOP(2),                 /* [0x34] */
501 	LRI(2, POSTED),         /* [0x36] */
502 	REG16(0x5a8),           /* [0x37] CONTEXT_SCHEDULING_ATTRIBUTES */
503 	REG16(0x5ac),           /* [0x39] PREEMPTION_STATUS */
505 	NOP(6),                 /* [0x41] */
506 	LRI(1, 0),              /* [0x47] */
507 	REG(0x0c8),             /* [0x48] R_PWR_CLK_STATE */
509 	0
515 	NOP(4 + 8 + 1),         /* [0x34] */
516 	LRI(2, POSTED),         /* [0x41] */
517 	REG16(0x200),           /* [0x42] BCS_SWCTRL */
518 	REG16(0x204),           /* [0x44] BLIT_CCTL */
520 	0
526 	0
530 	NOP(1),                 /* [0x00] */
531 	LRI(5, POSTED),         /* [0x01] */
532 	REG(0x034),             /* [0x02] RING_BUFFER_HEAD */
533 	REG(0x030),             /* [0x04] RING_BUFFER_TAIL */
534 	REG(0x038),             /* [0x06] RING_BUFFER_START */
535 	REG(0x048),             /* [0x08] RING_BUFFER_START_UDW */
536 	REG(0x03c),             /* [0x0a] RING_BUFFER_CONTROL */
538 	NOP(5),                 /* [0x0c] */
539 	LRI(9, POSTED),         /* [0x11] */
540 	REG(0x168),             /* [0x12] BB_ADDR_UDW */
541 	REG(0x140),             /* [0x14] BB_ADDR */
542 	REG(0x110),             /* [0x16] BB_STATE */
543 	REG16(0x588),           /* [0x18] BB_STACK_WRITE_PORT */
544 	REG16(0x588),           /* [0x20] BB_STACK_WRITE_PORT */
545 	REG16(0x588),           /* [0x22] BB_STACK_WRITE_PORT */
546 	REG16(0x588),           /* [0x24] BB_STACK_WRITE_PORT */
547 	REG16(0x588),           /* [0x26] BB_STACK_WRITE_PORT */
548 	REG16(0x588),           /* [0x28] BB_STACK_WRITE_PORT */
550 	NOP(12),                 /* [0x00] */
552 	0
610 	regs[CTX_INT_MASK_ENABLE_REG] = RING_IMR(0).addr;  in set_memory_based_intr()
615 	regs[CTX_INT_STATUS_REPORT_REG] = RING_INT_STATUS_RPT_PTR(0).addr;  in set_memory_based_intr()
617 	regs[CTX_INT_SRC_REPORT_REG] = RING_INT_SRC_RPT_PTR(0).addr;  in set_memory_based_intr()
626 		return 0x70;  in lrc_ring_mi_mode()
628 		return 0x60;  in lrc_ring_mi_mode()
647 	return 0;  in __xe_lrc_ring_offset()
804 		return 0;  in xe_lrc_indirect_ring_ggtt_addr()
892 #define PVC_CTX_ASID		(0x2e + 1)
893 #define PVC_CTX_ACC_CTR_THOLD	(0x2a + 1)
908 	lrc->flags = 0;  in xe_lrc_init()
928 	lrc->ring.tail = 0;  in xe_lrc_init()
929 	lrc->ctx_timestamp = 0;  in xe_lrc_init()
948 		xe_map_memset(xe, &map, 0, 0, LRC_PPHWSP_SIZE);	/* PPHWSP */  in xe_lrc_init()
953 		xe_map_memcpy_to(xe, &map, 0, init_data,  in xe_lrc_init()
971 		xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_START_UDW, 0);  in xe_lrc_init()
972 		xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_HEAD, 0);  in xe_lrc_init()
978 		xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, 0);  in xe_lrc_init()
984 	xe_lrc_write_ctx_reg(lrc, CTX_TIMESTAMP, 0);  in xe_lrc_init()
1013 	return 0;  in xe_lrc_init()
1054  * Called when ref == 0, release resources held by the Logical Ring Context
1112 	xe_map_memcpy_to(xe, &ring, 0, data, size);  in __xe_lrc_write_ring()
1226 	    GFXPIPE_SINGLE_DW_CMD(0, 0))  in instr_dw()
1233 	/* Most instructions have the # of dwords (minus 2) in 7:0 */  in instr_dw()
1285 			   dw[0] & MI_LRI_LRM_CS_MMIO ? "CS_MMIO " : "",  in dump_mi_command()
1286 			   dw[0] & MI_LRM_USE_GGTT ? "USE_GGTT " : "");  in dump_mi_command()
1502 	while (remaining_dw > 0) {  in xe_lrc_dump_default()
1584 	int state_table_size = 0;  in xe_lrc_emit_hwe_state_instructions()
1590 	 * setting up the default LRC, the context switch will write 0's  in xe_lrc_emit_hwe_state_instructions()
1617 	for (int i = 0; i < state_table_size; i++) {  in xe_lrc_emit_hwe_state_instructions()
1623 		xe_gt_assert(gt, num_dw != 0);  in xe_lrc_emit_hwe_state_instructions()
1712 	drm_printf(p, "\tHW Context Desc: 0x%08x\n", snapshot->context_desc);  in xe_lrc_snapshot_print()
1713 	drm_printf(p, "\tHW Indirect Ring State: 0x%08x\n",  in xe_lrc_snapshot_print()
1720 	drm_printf(p, "\tTimestamp: 0x%08x\n", snapshot->ctx_timestamp);  in xe_lrc_snapshot_print()
1721 	drm_printf(p, "\tJob Timestamp: 0x%08x\n", snapshot->ctx_job_timestamp);  in xe_lrc_snapshot_print()
1726 	drm_printf(p, "\t[HWSP].length: 0x%x\n", LRC_PPHWSP_SIZE);  in xe_lrc_snapshot_print()
1728 	for (i = 0; i < LRC_PPHWSP_SIZE; i += sizeof(u32)) {  in xe_lrc_snapshot_print()
1735 	drm_printf(p, "\n\t[HWCTX].length: 0x%lx\n", snapshot->lrc_size - LRC_PPHWSP_SIZE);  in xe_lrc_snapshot_print()