Lines Matching refs:xe_mmio_write32
43 xe_mmio_write32(mmio, reg, 0xffffffff); in assert_iir_is_zero()
45 xe_mmio_write32(mmio, reg, 0xffffffff); in assert_iir_is_zero()
63 xe_mmio_write32(mmio, IER(irqregs), bits); in unmask_and_enable()
64 xe_mmio_write32(mmio, IMR(irqregs), ~bits); in unmask_and_enable()
75 xe_mmio_write32(mmio, IMR(irqregs), ~0); in mask_and_disable()
79 xe_mmio_write32(mmio, IER(irqregs), 0); in mask_and_disable()
82 xe_mmio_write32(mmio, IIR(irqregs), ~0); in mask_and_disable()
84 xe_mmio_write32(mmio, IIR(irqregs), ~0); in mask_and_disable()
92 xe_mmio_write32(mmio, GFX_MSTR_IRQ, 0); in xelp_intr_disable()
114 xe_mmio_write32(mmio, IIR(GU_MISC_IRQ_OFFSET), iir); in gu_misc_irq_ack()
123 xe_mmio_write32(mmio, GFX_MSTR_IRQ, MASTER_IRQ); in xelp_intr_enable()
158 xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, dmask); in xe_irq_enable_hwe()
160 xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, smask); in xe_irq_enable_hwe()
163 xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~smask); in xe_irq_enable_hwe()
164 xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~smask); in xe_irq_enable_hwe()
166 xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
168 xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
170 xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
172 xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
174 xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
176 xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
181 xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, dmask); in xe_irq_enable_hwe()
184 xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
185 xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
186 xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
200 xe_mmio_write32(gt, GUNIT_GSC_INTR_ENABLE, gsc_mask | heci_mask); in xe_irq_enable_hwe()
201 xe_mmio_write32(gt, GUNIT_GSC_INTR_MASK, ~gsc_mask); in xe_irq_enable_hwe()
204 xe_mmio_write32(gt, HECI2_RSVD_INTR_MASK, ~(heci_mask << 16)); in xe_irq_enable_hwe()
219 xe_mmio_write32(mmio, IIR_REG_SELECTOR(bank), BIT(bit)); in gt_engine_identity()
237 xe_mmio_write32(mmio, INTR_IDENTITY_REG(bank), ident); in gt_engine_identity()
309 xe_mmio_write32(mmio, GT_INTR_DW(bank), intr_dw[bank]); in gt_irq_handler()
383 xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, 0); in dg1_intr_disable()
390 xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, val); in dg1_intr_disable()
399 xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ); in dg1_intr_enable()
452 xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl); in dg1_irq_handler()
485 xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, 0); in gt_irq_reset()
486 xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, 0); in gt_irq_reset()
488 xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, 0); in gt_irq_reset()
491 xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~0); in gt_irq_reset()
492 xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~0); in gt_irq_reset()
494 xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~0); in gt_irq_reset()
496 xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~0); in gt_irq_reset()
498 xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~0); in gt_irq_reset()
500 xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~0); in gt_irq_reset()
501 xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~0); in gt_irq_reset()
502 xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~0); in gt_irq_reset()
503 xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~0); in gt_irq_reset()
505 xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~0); in gt_irq_reset()
507 xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~0); in gt_irq_reset()
512 xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, 0); in gt_irq_reset()
513 xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~0); in gt_irq_reset()
514 xe_mmio_write32(mmio, HECI2_RSVD_INTR_MASK, ~0); in gt_irq_reset()
517 xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0); in gt_irq_reset()
518 xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK, ~0); in gt_irq_reset()
519 xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE, 0); in gt_irq_reset()
520 xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0); in gt_irq_reset()
552 xe_mmio_write32(mmio, GFX_MSTR_IRQ, ~0); in dg1_irq_reset_mstr()