Lines Matching full:tile

53 static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits)  in unmask_and_enable()  argument
55 struct xe_gt *mmio = tile->primary_gt; in unmask_and_enable()
71 static void mask_and_disable(struct xe_tile *tile, u32 irqregs) in mask_and_disable() argument
73 struct xe_gt *mmio = tile->primary_gt; in mask_and_disable()
261 static struct xe_gt *pick_engine_gt(struct xe_tile *tile, in pick_engine_gt() argument
265 struct xe_device *xe = tile_to_xe(tile); in pick_engine_gt()
268 return tile->primary_gt; in pick_engine_gt()
273 return tile->media_gt; in pick_engine_gt()
279 return tile->media_gt; in pick_engine_gt()
285 return tile->primary_gt; in pick_engine_gt()
289 static void gt_irq_handler(struct xe_tile *tile, in gt_irq_handler() argument
293 struct xe_device *xe = tile_to_xe(tile); in gt_irq_handler()
294 struct xe_gt *mmio = tile->primary_gt; in gt_irq_handler()
318 engine_gt = pick_engine_gt(tile, class, instance); in gt_irq_handler()
341 * a "master tile" interrupt register.
346 struct xe_tile *tile = xe_device_get_root_tile(xe); in xelp_irq_handler() local
364 gt_irq_handler(tile, master_ctl, intr_dw, identity); in xelp_irq_handler()
406 * a "master tile" interrupt register which must be consulted before the
412 struct xe_tile *tile; in dg1_irq_handler() local
433 for_each_tile(tile, xe, id) { in dg1_irq_handler()
434 struct xe_gt *mmio = tile->primary_gt; in dg1_irq_handler()
436 if ((master_tile_ctl & DG1_MSTR_TILE(tile->id)) == 0) in dg1_irq_handler()
447 drm_dbg(&tile_to_xe(tile)->drm, in dg1_irq_handler()
454 gt_irq_handler(tile, master_ctl, intr_dw, identity); in dg1_irq_handler()
459 * the primary tile. in dg1_irq_handler()
475 static void gt_irq_reset(struct xe_tile *tile) in gt_irq_reset() argument
477 struct xe_gt *mmio = tile->primary_gt; in gt_irq_reset()
479 u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, in gt_irq_reset()
481 u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, in gt_irq_reset()
509 if ((tile->media_gt && in gt_irq_reset()
510 xe_hw_engine_mask_per_class(tile->media_gt, XE_ENGINE_CLASS_OTHER)) || in gt_irq_reset()
511 HAS_HECI_GSCFI(tile_to_xe(tile))) { in gt_irq_reset()
523 static void xelp_irq_reset(struct xe_tile *tile) in xelp_irq_reset() argument
525 xelp_intr_disable(tile_to_xe(tile)); in xelp_irq_reset()
527 gt_irq_reset(tile); in xelp_irq_reset()
529 if (IS_SRIOV_VF(tile_to_xe(tile))) in xelp_irq_reset()
532 mask_and_disable(tile, PCU_IRQ_OFFSET); in xelp_irq_reset()
535 static void dg1_irq_reset(struct xe_tile *tile) in dg1_irq_reset() argument
537 if (tile->id == 0) in dg1_irq_reset()
538 dg1_intr_disable(tile_to_xe(tile)); in dg1_irq_reset()
540 gt_irq_reset(tile); in dg1_irq_reset()
542 if (IS_SRIOV_VF(tile_to_xe(tile))) in dg1_irq_reset()
545 mask_and_disable(tile, PCU_IRQ_OFFSET); in dg1_irq_reset()
548 static void dg1_irq_reset_mstr(struct xe_tile *tile) in dg1_irq_reset_mstr() argument
550 struct xe_gt *mmio = tile->primary_gt; in dg1_irq_reset_mstr()
557 struct xe_tile *tile; in vf_irq_reset() local
567 for_each_tile(tile, xe, id) { in vf_irq_reset()
569 xe_memirq_reset(&tile->sriov.vf.memirq); in vf_irq_reset()
571 gt_irq_reset(tile); in vf_irq_reset()
577 struct xe_tile *tile; in xe_irq_reset() local
583 for_each_tile(tile, xe, id) { in xe_irq_reset()
585 dg1_irq_reset(tile); in xe_irq_reset()
587 xelp_irq_reset(tile); in xe_irq_reset()
590 tile = xe_device_get_root_tile(xe); in xe_irq_reset()
591 mask_and_disable(tile, GU_MISC_IRQ_OFFSET); in xe_irq_reset()
595 * The tile's top-level status register should be the last one in xe_irq_reset()
600 for_each_tile(tile, xe, id) in xe_irq_reset()
601 dg1_irq_reset_mstr(tile); in xe_irq_reset()
607 struct xe_tile *tile; in vf_irq_postinstall() local
610 for_each_tile(tile, xe, id) in vf_irq_postinstall()
612 xe_memirq_postinstall(&tile->sriov.vf.memirq); in vf_irq_postinstall()
629 * on the root tile. in xe_irq_postinstall()
644 struct xe_tile *tile; in vf_mem_irq_handler() local
654 for_each_tile(tile, xe, id) in vf_mem_irq_handler()
655 xe_memirq_handler(&tile->sriov.vf.memirq); in vf_mem_irq_handler()