Lines Matching refs:mmio_base
48 u32 mmio_base; member
58 .mmio_base = RENDER_RING_BASE,
66 .mmio_base = BLT_RING_BASE,
74 .mmio_base = XEHPC_BCS1_RING_BASE,
82 .mmio_base = XEHPC_BCS2_RING_BASE,
90 .mmio_base = XEHPC_BCS3_RING_BASE,
98 .mmio_base = XEHPC_BCS4_RING_BASE,
106 .mmio_base = XEHPC_BCS5_RING_BASE,
114 .mmio_base = XEHPC_BCS6_RING_BASE,
122 .mmio_base = XEHPC_BCS7_RING_BASE,
130 .mmio_base = XEHPC_BCS8_RING_BASE,
139 .mmio_base = BSD_RING_BASE,
147 .mmio_base = BSD2_RING_BASE,
155 .mmio_base = BSD3_RING_BASE,
163 .mmio_base = BSD4_RING_BASE,
171 .mmio_base = XEHP_BSD5_RING_BASE,
179 .mmio_base = XEHP_BSD6_RING_BASE,
187 .mmio_base = XEHP_BSD7_RING_BASE,
195 .mmio_base = XEHP_BSD8_RING_BASE,
203 .mmio_base = VEBOX_RING_BASE,
211 .mmio_base = VEBOX2_RING_BASE,
219 .mmio_base = XEHP_VEBOX3_RING_BASE,
227 .mmio_base = XEHP_VEBOX4_RING_BASE,
235 .mmio_base = COMPUTE0_RING_BASE,
243 .mmio_base = COMPUTE1_RING_BASE,
251 .mmio_base = COMPUTE2_RING_BASE,
259 .mmio_base = COMPUTE3_RING_BASE,
266 .mmio_base = GSCCS_RING_BASE,
293 xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); in xe_hw_engine_mmio_write32()
296 reg.addr += hwe->mmio_base; in xe_hw_engine_mmio_write32()
313 xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); in xe_hw_engine_mmio_read32()
316 reg.addr += hwe->mmio_base; in xe_hw_engine_mmio_read32()
481 hwe->mmio_base = info->mmio_base; in hw_engine_init_early()
905 snapshot->mmio_base = hwe->mmio_base; in xe_hw_engine_snapshot_capture()
1153 return xe_mmio_read64_2x32(hwe->gt, RING_TIMESTAMP(hwe->mmio_base)); in xe_hw_engine_read_timestamp()