Lines Matching +full:0 +full:xc304
16 #define DIST_DBS_POPULATED XE_REG(0xd08)
18 #define SQIDIS_DOORBELL_EXIST_MASK REG_GENMASK(15, 0)
20 #define DRBREGL(x) XE_REG(0x1000 + (x) * 8)
21 #define DRB_VALID REG_BIT(0)
22 #define DRBREGU(x) XE_REG(0x1000 + (x) * 8 + 4)
24 #define GTCR XE_REG(0x4274)
25 #define GTCR_INVALIDATE REG_BIT(0)
27 #define GUC_ARAT_C6DIS XE_REG(0xa178)
29 #define GUC_STATUS XE_REG(0xc000)
31 #define GS_AUTH_STATUS_BAD REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x1)
32 #define GS_AUTH_STATUS_GOOD REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x2)
34 #define GS_MIA_CORE_STATE REG_FIELD_PREP(GS_MIA_MASK, 0x1)
35 #define GS_MIA_HALT_REQUESTED REG_FIELD_PREP(GS_MIA_MASK, 0x2)
36 #define GS_MIA_ISR_ENTRY REG_FIELD_PREP(GS_MIA_MASK, 0x4)
39 #define GS_BOOTROM_RSA_FAILED REG_FIELD_PREP(GS_BOOTROM_MASK, 0x50)
40 #define GS_BOOTROM_JUMP_PASSED REG_FIELD_PREP(GS_BOOTROM_MASK, 0x76)
41 #define GS_MIA_IN_RESET REG_BIT(0)
43 #define GUC_HEADER_INFO XE_REG(0xc014)
45 #define GUC_WOPCM_SIZE XE_REG(0xc050)
47 #define GUC_WOPCM_SIZE_LOCKED REG_BIT(0)
49 #define GUC_SHIM_CONTROL XE_REG(0xc064)
58 #define GUC_DISABLE_SRAM_INIT_TO_ZEROES REG_BIT(0)
60 #define SOFT_SCRATCH(n) XE_REG(0xc180 + (n) * 4)
63 #define HUC_KERNEL_LOAD_INFO XE_REG(0xc1dc)
64 #define HUC_LOAD_SUCCESSFUL REG_BIT(0)
66 #define UOS_RSA_SCRATCH(i) XE_REG(0xc200 + (i) * 4)
69 #define DMA_ADDR_0_LOW XE_REG(0xc300)
70 #define DMA_ADDR_0_HIGH XE_REG(0xc304)
71 #define DMA_ADDR_1_LOW XE_REG(0xc308)
72 #define DMA_ADDR_1_HIGH XE_REG(0xc30c)
76 #define DMA_COPY_SIZE XE_REG(0xc310)
77 #define DMA_CTRL XE_REG(0xc314)
80 #define START_DMA REG_BIT(0)
81 #define DMA_GUC_WOPCM_OFFSET XE_REG(0xc340)
85 #define GUC_WOPCM_OFFSET_VALID REG_BIT(0)
86 #define GUC_MAX_IDLE_COUNT XE_REG(0xc3e4)
88 #define GUC_SEND_INTERRUPT XE_REG(0xc4c8)
89 #define GUC_SEND_TRIGGER REG_BIT(0)
91 #define GUC_BCS_RCS_IER XE_REG(0xc550)
92 #define GUC_VCS2_VCS1_IER XE_REG(0xc554)
93 #define GUC_WD_VECS_IER XE_REG(0xc558)
94 #define GUC_PM_P24C_IER XE_REG(0xc55c)
96 #define GUC_TLB_INV_CR XE_REG(0xcee8)
97 #define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
99 #define HUC_STATUS2 XE_REG(0xd3b0)
102 #define GT_PM_CONFIG XE_REG(0x13816c)
103 #define GT_DOORBELL_ENABLE REG_BIT(0)
105 #define GUC_HOST_INTERRUPT XE_REG(0x1901f0, XE_REG_OPTION_VF)
107 #define VF_SW_FLAG(n) XE_REG(0x190240 + (n) * 4, XE_REG_OPTION_VF)
110 #define MED_GUC_HOST_INTERRUPT XE_REG(0x190304, XE_REG_OPTION_VF)
112 #define MED_VF_SW_FLAG(n) XE_REG(0x190310 + (n) * 4, XE_REG_OPTION_VF)
115 #define GUC_TLB_INV_CR XE_REG(0xcee8)
116 #define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
117 #define PVC_GUC_TLB_INV_DESC0 XE_REG(0xcf7c)
118 #define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0)
119 #define PVC_GUC_TLB_INV_DESC1 XE_REG(0xcf80)
138 #define GUC_INTR_SW_INT_0 REG_BIT(0)
145 #define GUC_DOORBELL_DISABLED 0