Lines Matching refs:REG_GENMASK
21 #define MTL_CAGF_MASK REG_GENMASK(8, 0)
22 #define MTL_CC_MASK REG_GENMASK(12, 9)
26 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
31 #define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
38 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
39 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
40 #define GMD_ID_REVID REG_GENMASK(5, 0)
51 #define MCR_SLICE_MASK REG_GENMASK(30, 27)
53 #define MCR_SUBSLICE_MASK REG_GENMASK(26, 24)
55 #define MTL_MCR_GROUPID REG_GENMASK(11, 8)
56 #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
62 #define LE_SSE_MASK REG_GENMASK(18, 17)
64 #define LE_COS_MASK REG_GENMASK(16, 15)
68 #define LE_PFM_MASK REG_GENMASK(13, 11)
70 #define LE_SCC_MASK REG_GENMASK(10, 8)
76 #define LE_LRUM_MASK REG_GENMASK(5, 4)
78 #define LE_TGT_CACHE_MASK REG_GENMASK(3, 2)
80 #define LE_CACHEABILITY_MASK REG_GENMASK(1, 0)
84 #define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0)
101 #define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8)
115 #define VS_HIT_MAX_VALUE_MASK REG_GENMASK(25, 20)
127 #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
129 #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
175 #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
194 #define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK REG_GENMASK(31, 6)
197 #define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK REG_GENMASK(7, 0)
208 #define CCS_EN_MASK REG_GENMASK(19, 16)
209 #define GT_L3_EXC_MASK REG_GENMASK(6, 4)
212 #define XE2_NODE_ENABLE_MASK REG_GENMASK(31, 16)
214 #define XEHPC_GT_L3_MODE_MASK REG_GENMASK(7, 4)
215 #define XE2_GT_L3_MODE_MASK REG_GENMASK(7, 4)
216 #define L3BANK_MASK REG_GENMASK(3, 0)
217 #define XELP_GT_L3_MODE_MASK REG_GENMASK(7, 0)
220 #define MEML3_EN_MASK REG_GENMASK(3, 0)
225 #define XELP_EU_MASK REG_GENMASK(7, 0)
230 #define GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16)
231 #define GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0)
315 #define REQ_RATIO_MASK REG_GENMASK(31, 23)
318 #define RPSWCTL_MASK REG_GENMASK(10, 9)
343 #define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
360 #define L3_UPPER_IDX_CACHEABILITY_MASK REG_GENMASK(21, 20)
361 #define L3_UPPER_IDX_SCC_MASK REG_GENMASK(19, 17)
367 #define L3_CACHEABILITY_MASK REG_GENMASK(5, 4)
369 #define L3_SCC_MASK REG_GENMASK(3, 1)
387 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
427 #define LMTT_DIR_PTR REG_GENMASK(30, 0) /* in multiples of 64KB */
455 #define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
487 #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
504 #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
508 #define COMP_CKN_IN REG_GENMASK(30, 29)
521 #define CCS_MODE_CSLICE_0_3_MASK REG_GENMASK(11, 0) /* 3 bits per cslice */
538 #define RCN_MASK REG_GENMASK(2, 0)
557 #define VOLTAGE_MASK REG_GENMASK(10, 0)
579 #define ENGINE1_MASK REG_GENMASK(31, 16)
580 #define ENGINE0_MASK REG_GENMASK(15, 0)