49 	struct vmw_private *dev_priv = vmw_priv(du->primary.dev);  in vmw_du_cleanup()
747 	struct vmw_private *dev_priv = vmw_priv(crtc->dev);  in vmw_du_cursor_plane_atomic_update()
929 	struct vmw_private *vmw = vmw_priv(crtc->dev);  in vmw_du_crtc_atomic_check()
1495 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_kms_fb_create()
1553 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_kms_check_display_memory()
1894 	struct vmw_private *vmw = vmw_priv(old_state->dev);  in vmw_atomic_commit_tail()
2005 int vmw_kms_write_svga(struct vmw_private *vmw_priv,  in vmw_kms_write_svga()  argument
2009 	if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)  in vmw_kms_write_svga()
2010 		vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);  in vmw_kms_write_svga()
2011 	else if (vmw_fifo_have_pitchlock(vmw_priv))  in vmw_kms_write_svga()
2012 		vmw_fifo_mem_write(vmw_priv, SVGA_FIFO_PITCHLOCK, pitch);  in vmw_kms_write_svga()
2013 	vmw_write(vmw_priv, SVGA_REG_WIDTH, width);  in vmw_kms_write_svga()
2014 	vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);  in vmw_kms_write_svga()
2015 	if ((vmw_priv->capabilities & SVGA_CAP_8BIT_EMULATION) != 0)  in vmw_kms_write_svga()
2016 		vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);  in vmw_kms_write_svga()
2018 	if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {  in vmw_kms_write_svga()
2020 			  depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));  in vmw_kms_write_svga()
2121 	struct vmw_private *dev_priv = vmw_priv(crtc->dev);  in vmw_du_crtc_gamma_set()
2145 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_du_connector_detect()
2198 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_kms_update_layout_ioctl()
2470 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_kms_suspend()
2497 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_kms_resume()
2667 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_connector_mode_valid()
2697 	struct vmw_private *dev_priv = vmw_priv(dev);  in vmw_connector_get_modes()