Lines Matching refs:validation_state
156 struct vc4_shader_validation_state *validation_state, in record_texture_sample() argument
170 &validation_state->tmu_setup[tmu], in record_texture_sample()
177 validation_state->tmu_setup[tmu].p_offset[i] = ~0; in record_texture_sample()
184 struct vc4_shader_validation_state *validation_state, in check_tmu_write() argument
187 uint64_t inst = validation_state->shader[validation_state->ip]; in check_tmu_write()
195 bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0; in check_tmu_write()
227 clamp_offset = validation_state->live_min_clamp_offsets[clamp_reg]; in check_tmu_write()
236 validation_state->tmu_setup[tmu].p_offset[1] = in check_tmu_write()
245 validation_state->tmu_setup[tmu].is_direct = true; in check_tmu_write()
255 if (validation_state->tmu_write_count[tmu] >= 4) { in check_tmu_write()
260 validation_state->tmu_setup[tmu].p_offset[validation_state->tmu_write_count[tmu]] = in check_tmu_write()
262 validation_state->tmu_write_count[tmu]++; in check_tmu_write()
267 if (validation_state->needs_uniform_address_update) { in check_tmu_write()
277 validation_state, tmu)) { in check_tmu_write()
281 validation_state->tmu_write_count[tmu] = 0; in check_tmu_write()
308 struct vc4_shader_validation_state *validation_state, in validate_uniform_address_write() argument
311 uint64_t inst = validation_state->shader[validation_state->ip]; in validate_uniform_address_write()
366 if (validation_state->live_immediates[add_lri] != expected_offset) { in validate_uniform_address_write()
368 validation_state->live_immediates[add_lri], in validate_uniform_address_write()
380 validation_state->needs_uniform_address_update = false; in validate_uniform_address_write()
381 validation_state->needs_uniform_address_for_loop = false; in validate_uniform_address_write()
387 struct vc4_shader_validation_state *validation_state, in check_reg_write() argument
390 uint64_t inst = validation_state->shader[validation_state->ip]; in check_reg_write()
407 validation_state->live_immediates[lri] = in check_reg_write()
410 validation_state->live_immediates[lri] = ~0; in check_reg_write()
414 validation_state->all_registers_used = true; in check_reg_write()
426 validation_state, in check_reg_write()
445 return check_tmu_write(validated_shader, validation_state, in check_reg_write()
479 struct vc4_shader_validation_state *validation_state) in track_live_clamps() argument
481 uint64_t inst = validation_state->shader[validation_state->ip]; in track_live_clamps()
500 validation_state->live_max_clamp_regs[lri_add_a]); in track_live_clamps()
506 validation_state->live_max_clamp_regs[lri_mul] = false; in track_live_clamps()
507 validation_state->live_min_clamp_offsets[lri_mul] = ~0; in track_live_clamps()
510 validation_state->live_max_clamp_regs[lri_add] = false; in track_live_clamps()
511 validation_state->live_min_clamp_offsets[lri_add] = ~0; in track_live_clamps()
533 validation_state->live_max_clamp_regs[lri_add] = true; in track_live_clamps()
547 validation_state->live_min_clamp_offsets[lri_add] = in track_live_clamps()
554 struct vc4_shader_validation_state *validation_state) in check_instruction_writes() argument
556 uint64_t inst = validation_state->shader[validation_state->ip]; in check_instruction_writes()
566 ok = (check_reg_write(validated_shader, validation_state, false) && in check_instruction_writes()
567 check_reg_write(validated_shader, validation_state, true)); in check_instruction_writes()
569 track_live_clamps(validated_shader, validation_state); in check_instruction_writes()
577 struct vc4_shader_validation_state *validation_state, in check_branch() argument
585 validation_state->needs_uniform_address_for_loop = true; in check_branch()
592 validation_state->ip); in check_branch()
601 struct vc4_shader_validation_state *validation_state) in check_instruction_reads() argument
603 uint64_t inst = validation_state->shader[validation_state->ip]; in check_instruction_reads()
616 if (validation_state->needs_uniform_address_update) { in check_instruction_reads()
625 validation_state->all_registers_used = true; in check_instruction_reads()
635 vc4_validate_branches(struct vc4_shader_validation_state *validation_state) in vc4_validate_branches() argument
641 for (ip = 0; ip < validation_state->max_ip; ip++) { in vc4_validate_branches()
642 uint64_t inst = validation_state->shader[ip]; in vc4_validate_branches()
655 validation_state->max_ip = ip + 3; in vc4_validate_branches()
690 if (branch_target_ip >= validation_state->max_ip) { in vc4_validate_branches()
693 validation_state->max_ip); in vc4_validate_branches()
696 set_bit(branch_target_ip, validation_state->branch_targets); in vc4_validate_branches()
701 if (after_delay_ip >= validation_state->max_ip) { in vc4_validate_branches()
704 ip, after_delay_ip, validation_state->max_ip); in vc4_validate_branches()
707 set_bit(after_delay_ip, validation_state->branch_targets); in vc4_validate_branches()
711 if (max_branch_target > validation_state->max_ip - 3) { in vc4_validate_branches()
723 reset_validation_state(struct vc4_shader_validation_state *validation_state) in reset_validation_state() argument
728 validation_state->tmu_setup[i / 4].p_offset[i % 4] = ~0; in reset_validation_state()
731 validation_state->live_min_clamp_offsets[i] = ~0; in reset_validation_state()
732 validation_state->live_max_clamp_regs[i] = false; in reset_validation_state()
733 validation_state->live_immediates[i] = ~0; in reset_validation_state()
738 texturing_in_progress(struct vc4_shader_validation_state *validation_state) in texturing_in_progress() argument
740 return (validation_state->tmu_write_count[0] != 0 || in texturing_in_progress()
741 validation_state->tmu_write_count[1] != 0); in texturing_in_progress()
745 vc4_handle_branch_target(struct vc4_shader_validation_state *validation_state) in vc4_handle_branch_target() argument
747 uint32_t ip = validation_state->ip; in vc4_handle_branch_target()
749 if (!test_bit(ip, validation_state->branch_targets)) in vc4_handle_branch_target()
752 if (texturing_in_progress(validation_state)) { in vc4_handle_branch_target()
764 reset_validation_state(validation_state); in vc4_handle_branch_target()
773 validation_state->needs_uniform_address_update = true; in vc4_handle_branch_target()
787 struct vc4_shader_validation_state validation_state; in vc4_validate_shader() local
792 memset(&validation_state, 0, sizeof(validation_state)); in vc4_validate_shader()
793 validation_state.shader = shader_obj->vaddr; in vc4_validate_shader()
794 validation_state.max_ip = shader_obj->base.size / sizeof(uint64_t); in vc4_validate_shader()
796 reset_validation_state(&validation_state); in vc4_validate_shader()
798 validation_state.branch_targets = in vc4_validate_shader()
799 kcalloc(BITS_TO_LONGS(validation_state.max_ip), in vc4_validate_shader()
801 if (!validation_state.branch_targets) in vc4_validate_shader()
808 if (!vc4_validate_branches(&validation_state)) in vc4_validate_shader()
811 for (ip = 0; ip < validation_state.max_ip; ip++) { in vc4_validate_shader()
812 uint64_t inst = validation_state.shader[ip]; in vc4_validate_shader()
815 validation_state.ip = ip; in vc4_validate_shader()
817 if (!vc4_handle_branch_target(&validation_state)) in vc4_validate_shader()
825 validation_state.live_min_clamp_offsets[i] = ~0; in vc4_validate_shader()
826 validation_state.live_max_clamp_regs[i] = false; in vc4_validate_shader()
827 validation_state.live_immediates[i] = ~0; in vc4_validate_shader()
843 &validation_state)) { in vc4_validate_shader()
849 &validation_state)) in vc4_validate_shader()
873 &validation_state)) { in vc4_validate_shader()
881 &validation_state, ip)) in vc4_validate_shader()
904 if (ip == validation_state.max_ip) { in vc4_validate_shader()
913 validation_state.all_registers_used) { in vc4_validate_shader()
928 if (validation_state.needs_uniform_address_for_loop) { in vc4_validate_shader()
942 kfree(validation_state.branch_targets); in vc4_validate_shader()
947 kfree(validation_state.branch_targets); in vc4_validate_shader()