Lines Matching +full:30 +full:bpp

314 # define SCALER_DISPDITHER_DSP5_MUX_SHIFT	30
315 # define SCALER_DISPDITHER_DSP5_MUX_MASK	VC4_MASK(31, 30)
318 # define SCALER_DISPEOLN_DSP4_MUX_SHIFT		30
319 # define SCALER_DISPEOLN_DSP4_MUX_MASK		VC4_MASK(31, 30)
338 # define SCALER_DISPCTRLX_RESET			BIT(30)
347 /* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */
376 # define SCALER_DISPBKGND_INTERLACE		BIT(30)
387 # define SCALER_DISPSTATX_MODE_MASK		VC4_MASK(31, 30)
388 # define SCALER_DISPSTATX_MODE_SHIFT		30
447 # define SCALER_GAMADDR_SRAMENB			BIT(30)
501 # define SCALER_DISPSLAVE_ISSUE_HSTART          BIT(30)
642 # define VC4_HDMI_CEC_TX_STATUS_GOOD		BIT(30)
676 # define VC4_HDMI_CEC_CNT_TO_1500_US_MASK	VC4_MASK(30, 24)
773 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE	BIT(30)
823 	/* 8bpp */
825 	/* 16bpp */
830 	/* 24bpp */
833 	/* 32bpp */
870 #define SCALER_CTL0_VALID			BIT(30)
949 #define SCALER5_CTL2_ALPHA_MODE_MASK		VC4_MASK(31, 30)
950 #define SCALER5_CTL2_ALPHA_MODE_SHIFT		30
982 #define SCALER_POS2_ALPHA_MODE_MASK		VC4_MASK(31, 30)
983 #define SCALER_POS2_ALPHA_MODE_SHIFT		30
1076 #define SCALER_PPF_AGC				BIT(30)