Lines Matching +full:assigned +full:- +full:resolution +full:- +full:bits
1 // SPDX-License-Identifier: GPL-2.0-only
49 struct drm_device *dev = state->dev; in vc4_get_ctm_state()
54 ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx); in vc4_get_ctm_state()
70 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in vc4_ctm_duplicate_state()
74 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in vc4_ctm_duplicate_state()
76 return &state->base; in vc4_ctm_duplicate_state()
96 drm_atomic_private_obj_fini(&vc4->ctm_manager); in vc4_ctm_obj_fini()
103 drm_modeset_lock_init(&vc4->ctm_state_lock); in vc4_ctm_obj_init()
107 return -ENOMEM; in vc4_ctm_obj_init()
109 drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base, in vc4_ctm_obj_init()
112 return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL); in vc4_ctm_obj_init()
124 /* We have zero integer bits so we can only saturate here. */ in vc4_ctm_s31_32_to_s0_9()
127 /* Otherwise take the 9 most important fractional bits. */ in vc4_ctm_s31_32_to_s0_9()
137 struct vc4_hvs *hvs = vc4->hvs; in vc4_ctm_commit()
138 struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state); in vc4_ctm_commit()
139 struct drm_color_ctm *ctm = ctm_state->ctm; in vc4_ctm_commit()
141 if (ctm_state->fifo) { in vc4_ctm_commit()
143 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), in vc4_ctm_commit()
145 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), in vc4_ctm_commit()
147 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), in vc4_ctm_commit()
150 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), in vc4_ctm_commit()
152 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), in vc4_ctm_commit()
154 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), in vc4_ctm_commit()
157 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), in vc4_ctm_commit()
159 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), in vc4_ctm_commit()
161 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), in vc4_ctm_commit()
166 VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO)); in vc4_ctm_commit()
172 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_hvs_get_new_global_state()
175 priv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels); in vc4_hvs_get_new_global_state()
177 return ERR_PTR(-EINVAL); in vc4_hvs_get_new_global_state()
185 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_hvs_get_old_global_state()
188 priv_state = drm_atomic_get_old_private_obj_state(state, &vc4->hvs_channels); in vc4_hvs_get_old_global_state()
190 return ERR_PTR(-EINVAL); in vc4_hvs_get_old_global_state()
198 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_hvs_get_global_state()
201 priv_state = drm_atomic_get_private_obj_state(state, &vc4->hvs_channels); in vc4_hvs_get_global_state()
211 struct vc4_hvs *hvs = vc4->hvs; in vc4_hvs_pv_muxing_commit()
222 if (!crtc_state->active) in vc4_hvs_pv_muxing_commit()
225 if (vc4_state->assigned_channel != 2) in vc4_hvs_pv_muxing_commit()
235 * TXP IP, and we need to disable the FIFO2 -> pixelvalve1 in vc4_hvs_pv_muxing_commit()
238 if (vc4_crtc->feeds_txp) in vc4_hvs_pv_muxing_commit()
252 struct vc4_hvs *hvs = vc4->hvs; in vc5_hvs_pv_muxing_commit()
262 unsigned int channel = vc4_state->assigned_channel; in vc5_hvs_pv_muxing_commit()
264 if (!vc4_state->update_muxing) in vc5_hvs_pv_muxing_commit()
267 switch (vc4_crtc->data->hvs_output) { in vc5_hvs_pv_muxing_commit()
269 drm_WARN_ON(&vc4->base, in vc5_hvs_pv_muxing_commit()
325 struct drm_device *dev = state->dev; in vc4_atomic_commit_tail()
327 struct vc4_hvs *hvs = vc4->hvs; in vc4_atomic_commit_tail()
346 if (!new_crtc_state->commit) in vc4_atomic_commit_tail()
350 vc4_hvs_mask_underrun(hvs, vc4_crtc_state->assigned_channel); in vc4_atomic_commit_tail()
357 if (!old_hvs_state->fifo_state[channel].in_use) in vc4_atomic_commit_tail()
360 commit = old_hvs_state->fifo_state[channel].pending_commit; in vc4_atomic_commit_tail()
369 old_hvs_state->fifo_state[channel].pending_commit = NULL; in vc4_atomic_commit_tail()
372 if (vc4->is_vc5) { in vc4_atomic_commit_tail()
373 unsigned long state_rate = max(old_hvs_state->core_clock_rate, in vc4_atomic_commit_tail()
374 new_hvs_state->core_clock_rate); in vc4_atomic_commit_tail()
376 500000000, hvs->max_core_rate); in vc4_atomic_commit_tail()
384 WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); in vc4_atomic_commit_tail()
391 if (vc4->is_vc5) in vc4_atomic_commit_tail()
409 if (vc4->is_vc5) { in vc4_atomic_commit_tail()
411 hvs->max_core_rate, in vc4_atomic_commit_tail()
412 new_hvs_state->core_clock_rate); in vc4_atomic_commit_tail()
420 WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); in vc4_atomic_commit_tail()
423 clk_get_rate(hvs->core_clk)); in vc4_atomic_commit_tail()
442 vc4_crtc_state->assigned_channel; in vc4_atomic_commit_setup()
447 if (!hvs_state->fifo_state[channel].in_use) in vc4_atomic_commit_setup()
450 hvs_state->fifo_state[channel].pending_commit = in vc4_atomic_commit_setup()
451 drm_crtc_commit_get(crtc_state->commit); in vc4_atomic_commit_setup()
464 if (WARN_ON_ONCE(vc4->is_vc5)) in vc4_fb_create()
465 return ERR_PTR(-ENODEV); in vc4_fb_create()
470 if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) { in vc4_fb_create()
475 mode_cmd->handles[0]); in vc4_fb_create()
478 mode_cmd->handles[0]); in vc4_fb_create()
479 return ERR_PTR(-ENOENT); in vc4_fb_create()
485 if (bo->t_format) { in vc4_fb_create()
516 if (!new_crtc_state->ctm && old_crtc_state->ctm) { in vc4_ctm_atomic_check()
517 ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); in vc4_ctm_atomic_check()
520 ctm_state->fifo = 0; in vc4_ctm_atomic_check()
525 if (new_crtc_state->ctm == old_crtc_state->ctm) in vc4_ctm_atomic_check()
529 ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); in vc4_ctm_atomic_check()
535 if (new_crtc_state->ctm) { in vc4_ctm_atomic_check()
539 /* fifo is 1-based since 0 disables CTM. */ in vc4_ctm_atomic_check()
540 int fifo = vc4_crtc_state->assigned_channel + 1; in vc4_ctm_atomic_check()
545 if (ctm_state->fifo && ctm_state->fifo != fifo) { in vc4_ctm_atomic_check()
547 return -EINVAL; in vc4_ctm_atomic_check()
552 * no integer bits. in vc4_ctm_atomic_check()
554 ctm = new_crtc_state->ctm->data; in vc4_ctm_atomic_check()
555 for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) { in vc4_ctm_atomic_check()
556 u64 val = ctm->matrix[i]; in vc4_ctm_atomic_check()
560 return -EINVAL; in vc4_ctm_atomic_check()
563 ctm_state->fifo = fifo; in vc4_ctm_atomic_check()
564 ctm_state->ctm = ctm; in vc4_ctm_atomic_check()
574 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_load_tracker_atomic_check()
581 &vc4->load_tracker); in vc4_load_tracker_atomic_check()
590 if (old_plane_state->fb && old_plane_state->crtc) { in vc4_load_tracker_atomic_check()
592 load_state->membus_load -= vc4_plane_state->membus_load; in vc4_load_tracker_atomic_check()
593 load_state->hvs_load -= vc4_plane_state->hvs_load; in vc4_load_tracker_atomic_check()
596 if (new_plane_state->fb && new_plane_state->crtc) { in vc4_load_tracker_atomic_check()
598 load_state->membus_load += vc4_plane_state->membus_load; in vc4_load_tracker_atomic_check()
599 load_state->hvs_load += vc4_plane_state->hvs_load; in vc4_load_tracker_atomic_check()
604 if (!vc4->load_tracker_enabled) in vc4_load_tracker_atomic_check()
610 if (load_state->membus_load > SZ_1G + SZ_512M) in vc4_load_tracker_atomic_check()
611 return -ENOSPC; in vc4_load_tracker_atomic_check()
616 if (load_state->hvs_load > 240000000ULL) in vc4_load_tracker_atomic_check()
617 return -ENOSPC; in vc4_load_tracker_atomic_check()
627 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in vc4_load_tracker_duplicate_state()
631 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in vc4_load_tracker_duplicate_state()
633 return &state->base; in vc4_load_tracker_duplicate_state()
654 drm_atomic_private_obj_fini(&vc4->load_tracker); in vc4_load_tracker_obj_fini()
663 return -ENOMEM; in vc4_load_tracker_obj_init()
665 drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker, in vc4_load_tracker_obj_init()
666 &load_state->base, in vc4_load_tracker_obj_init()
669 return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL); in vc4_load_tracker_obj_init()
675 struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state); in vc4_hvs_channels_duplicate_state()
683 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in vc4_hvs_channels_duplicate_state()
686 state->fifo_state[i].in_use = old_state->fifo_state[i].in_use; in vc4_hvs_channels_duplicate_state()
687 state->fifo_state[i].fifo_load = old_state->fifo_state[i].fifo_load; in vc4_hvs_channels_duplicate_state()
690 state->core_clock_rate = old_state->core_clock_rate; in vc4_hvs_channels_duplicate_state()
692 return &state->base; in vc4_hvs_channels_duplicate_state()
702 if (!hvs_state->fifo_state[i].pending_commit) in vc4_hvs_channels_destroy_state()
705 drm_crtc_commit_put(hvs_state->fifo_state[i].pending_commit); in vc4_hvs_channels_destroy_state()
718 drm_printf(p, "\tCore Clock Rate: %lu\n", hvs_state->core_clock_rate); in vc4_hvs_channels_print_state()
722 drm_printf(p, "\t\tin use=%d\n", hvs_state->fifo_state[i].in_use); in vc4_hvs_channels_print_state()
723 drm_printf(p, "\t\tload=%lu\n", hvs_state->fifo_state[i].fifo_load); in vc4_hvs_channels_print_state()
737 drm_atomic_private_obj_fini(&vc4->hvs_channels); in vc4_hvs_channels_obj_fini()
746 return -ENOMEM; in vc4_hvs_channels_obj_init()
748 drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels, in vc4_hvs_channels_obj_init()
749 &state->base, in vc4_hvs_channels_obj_init()
752 return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL); in vc4_hvs_channels_obj_init()
766 return data_a->hvs_output - data_b->hvs_output; in cmp_vc4_crtc_hvs_output()
778 * - When running in a dual-display setup (so with two CRTCs involved),
785 * - To fix the above, we can't use drm_atomic_get_crtc_state on all
791 * doing a modetest -v first on HDMI1 and then on HDMI0.
793 * - Since we need the pixelvalve to be disabled and enabled back when
794 * the FIFO is changed, we should keep the FIFO assigned for as long
797 * single display, and changing the resolution down and then back up.
813 for (i = 0; i < ARRAY_SIZE(hvs_new_state->fifo_state); i++) in vc4_pv_muxing_atomic_check()
814 if (!hvs_new_state->fifo_state[i].in_use) in vc4_pv_muxing_atomic_check()
832 * multiple routes is assigned one that was the only option for in vc4_pv_muxing_atomic_check()
838 sorted_crtcs = kmalloc_array(dev->num_crtcs, sizeof(*sorted_crtcs), GFP_KERNEL); in vc4_pv_muxing_atomic_check()
840 return -ENOMEM; in vc4_pv_muxing_atomic_check()
848 for (i = 0; i < dev->num_crtcs; i++) { in vc4_pv_muxing_atomic_check()
870 drm_dbg(dev, "%s: Trying to find a channel.\n", crtc->name); in vc4_pv_muxing_atomic_check()
873 if (old_crtc_state->enable == new_crtc_state->enable) { in vc4_pv_muxing_atomic_check()
874 if (new_crtc_state->enable) in vc4_pv_muxing_atomic_check()
876 crtc->name, new_vc4_crtc_state->assigned_channel); in vc4_pv_muxing_atomic_check()
878 drm_dbg(dev, "%s: Disabled, ignoring.\n", crtc->name); in vc4_pv_muxing_atomic_check()
884 new_vc4_crtc_state->update_muxing = true; in vc4_pv_muxing_atomic_check()
887 if (!new_crtc_state->enable) { in vc4_pv_muxing_atomic_check()
888 channel = old_vc4_crtc_state->assigned_channel; in vc4_pv_muxing_atomic_check()
891 crtc->name, channel); in vc4_pv_muxing_atomic_check()
893 hvs_new_state->fifo_state[channel].in_use = false; in vc4_pv_muxing_atomic_check()
894 new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; in vc4_pv_muxing_atomic_check()
898 matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels; in vc4_pv_muxing_atomic_check()
900 ret = -EINVAL; in vc4_pv_muxing_atomic_check()
904 channel = ffs(matching_channels) - 1; in vc4_pv_muxing_atomic_check()
906 drm_dbg(dev, "Assigned HVS channel %d to CRTC %s\n", channel, crtc->name); in vc4_pv_muxing_atomic_check()
907 new_vc4_crtc_state->assigned_channel = channel; in vc4_pv_muxing_atomic_check()
909 hvs_new_state->fifo_state[channel].in_use = true; in vc4_pv_muxing_atomic_check()
923 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_core_clock_atomic_check()
935 &vc4->load_tracker); in vc4_core_clock_atomic_check()
949 if (old_crtc_state->active) { in vc4_core_clock_atomic_check()
952 unsigned int channel = old_vc4_state->assigned_channel; in vc4_core_clock_atomic_check()
954 hvs_new_state->fifo_state[channel].fifo_load = 0; in vc4_core_clock_atomic_check()
957 if (new_crtc_state->active) { in vc4_core_clock_atomic_check()
960 unsigned int channel = new_vc4_state->assigned_channel; in vc4_core_clock_atomic_check()
962 hvs_new_state->fifo_state[channel].fifo_load = in vc4_core_clock_atomic_check()
963 new_vc4_state->hvs_load; in vc4_core_clock_atomic_check()
970 if (!hvs_new_state->fifo_state[i].in_use) in vc4_core_clock_atomic_check()
975 hvs_new_state->fifo_state[i].fifo_load, in vc4_core_clock_atomic_check()
979 pixel_rate = load_state->hvs_load; in vc4_core_clock_atomic_check()
986 hvs_new_state->core_clock_rate = max(cob_rate, pixel_rate); in vc4_core_clock_atomic_check()
1043 if (!vc4->is_vc5) { in vc4_kms_load()
1047 vc4->load_tracker_enabled = true; in vc4_kms_load()
1051 dev->vblank_disable_immediate = true; in vc4_kms_load()
1053 ret = drm_vblank_init(dev, dev->mode_config.num_crtc); in vc4_kms_load()
1055 dev_err(dev->dev, "failed to initialize vblank\n"); in vc4_kms_load()
1059 if (vc4->is_vc5) { in vc4_kms_load()
1060 dev->mode_config.max_width = 7680; in vc4_kms_load()
1061 dev->mode_config.max_height = 7680; in vc4_kms_load()
1063 dev->mode_config.max_width = 2048; in vc4_kms_load()
1064 dev->mode_config.max_height = 2048; in vc4_kms_load()
1067 dev->mode_config.funcs = vc4->is_vc5 ? &vc5_mode_funcs : &vc4_mode_funcs; in vc4_kms_load()
1068 dev->mode_config.helper_private = &vc4_mode_config_helpers; in vc4_kms_load()
1069 dev->mode_config.preferred_depth = 24; in vc4_kms_load()
1070 dev->mode_config.async_page_flip = true; in vc4_kms_load()
1071 dev->mode_config.normalize_zpos = true; in vc4_kms_load()