137 	struct vc4_hvs *hvs = vc4->hvs;  in vc4_ctm_commit()  local
211 	struct vc4_hvs *hvs = vc4->hvs;  in vc4_hvs_pv_muxing_commit()  local
252 	struct vc4_hvs *hvs = vc4->hvs;  in vc5_hvs_pv_muxing_commit()  local
327 	struct vc4_hvs *hvs = vc4->hvs;  in vc4_atomic_commit_tail()  local
350 		vc4_hvs_mask_underrun(hvs, vc4_crtc_state->assigned_channel);  in vc4_atomic_commit_tail()
376 						  500000000, hvs->max_core_rate);  in vc4_atomic_commit_tail()
384 		WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));  in vc4_atomic_commit_tail()
411 						hvs->max_core_rate,  in vc4_atomic_commit_tail()
417 		 * Request a clock rate based on the current HVS  in vc4_atomic_commit_tail()
420 		WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));  in vc4_atomic_commit_tail()
423 			clk_get_rate(hvs->core_clk));  in vc4_atomic_commit_tail()
613 	/* HVS clock is supposed to run @ 250Mhz, let's take a margin and  in vc4_load_tracker_atomic_check()
717 	drm_printf(p, "HVS State\n");  in vc4_hvs_channels_print_state()
770  * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and
822 	 * or 3 HVS FIFOs, and we need to set the muxing between FIFOs and  in vc4_pv_muxing_atomic_check()
823 	 * outputs in the HVS accordingly.  in vc4_pv_muxing_atomic_check()
906 		drm_dbg(dev, "Assigned HVS channel %d to CRTC %s\n", channel, crtc->name);  in vc4_pv_muxing_atomic_check()