drm/vc4/vc4_hdmi_regs.h

161 #define VC5_PHY_REG(reg, offset)	_VC4_REG(VC5_PHY, reg, offset)  macro
275 	VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
276 	VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
277 	VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
278 	VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
279 	VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
280 	VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
281 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
282 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
283 	VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
284 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
285 	VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
286 	VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
287 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
288 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
289 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
368 	VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
369 	VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
370 	VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
371 	VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
372 	VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
373 	VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
374 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
375 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
376 	VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
377 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
378 	VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
379 	VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
380 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
381 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
382 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),