Lines Matching refs:VC5_CSC_REG
159 #define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset) macro
311 VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
312 VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
313 VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
314 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
315 VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
316 VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
317 VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
318 VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
404 VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
405 VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
406 VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
407 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
408 VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
409 VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
410 VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
411 VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),