Lines Matching +full:bcm2835 +full:- +full:pm
1 // SPDX-License-Identifier: GPL-2.0-only
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
16 * This driver has been tested for DSI1 video-mode display only
21 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
146 * of going to LP-STOP.
149 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
151 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
153 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
539 /* Whether we're on bcm2835's DSI0 or DSI1. */
616 struct drm_device *drm = dsi->bridge.dev; in dsi_dma_workaround_write()
617 struct dma_chan *chan = dsi->reg_dma_chan; in dsi_dma_workaround_write()
626 writel(val, dsi->regs + offset); in dsi_dma_workaround_write()
630 *dsi->reg_dma_mem = val; in dsi_dma_workaround_write()
632 tx = chan->device->device_prep_dma_memcpy(chan, in dsi_dma_workaround_write()
633 dsi->reg_paddr + offset, in dsi_dma_workaround_write()
634 dsi->reg_dma_paddr, in dsi_dma_workaround_write()
641 cookie = tx->tx_submit(tx); in dsi_dma_workaround_write()
655 readl(dsi->regs + (offset)); \
660 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
662 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
663 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
730 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS; in vc4_dsi_ulps()
733 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | in vc4_dsi_ulps()
734 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | in vc4_dsi_ulps()
735 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); in vc4_dsi_ulps()
738 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | in vc4_dsi_ulps()
739 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | in vc4_dsi_ulps()
740 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); in vc4_dsi_ulps()
743 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | in vc4_dsi_ulps()
744 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | in vc4_dsi_ulps()
745 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); in vc4_dsi_ulps()
757 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
776 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
817 struct device *dev = &dsi->pdev->dev; in vc4_dsi_bridge_post_disable()
819 clk_disable_unprepare(dsi->pll_phy_clock); in vc4_dsi_bridge_post_disable()
820 clk_disable_unprepare(dsi->escape_clock); in vc4_dsi_bridge_post_disable()
821 clk_disable_unprepare(dsi->pixel_clock); in vc4_dsi_bridge_post_disable()
826 /* Extends the mode's blank intervals to handle BCM2835's integer-only
836 * higher-than-expected clock rate to the panel, but that's what the
844 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock); in vc4_dsi_bridge_mode_fixup()
846 unsigned long pixel_clock_hz = mode->clock * 1000; in vc4_dsi_bridge_mode_fixup()
847 unsigned long pll_clock = pixel_clock_hz * dsi->divider; in vc4_dsi_bridge_mode_fixup()
862 pixel_clock_hz = pll_clock / dsi->divider; in vc4_dsi_bridge_mode_fixup()
864 adjusted_mode->clock = pixel_clock_hz / 1000; in vc4_dsi_bridge_mode_fixup()
867 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal / in vc4_dsi_bridge_mode_fixup()
868 mode->clock; in vc4_dsi_bridge_mode_fixup()
869 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal; in vc4_dsi_bridge_mode_fixup()
870 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal; in vc4_dsi_bridge_mode_fixup()
878 struct drm_atomic_state *state = old_state->base.state; in vc4_dsi_bridge_pre_enable()
881 struct device *dev = &dsi->pdev->dev; in vc4_dsi_bridge_pre_enable()
897 drm_err(bridge->dev, "Failed to runtime PM enable on DSI%d\n", dsi->variant->port); in vc4_dsi_bridge_pre_enable()
902 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_bridge_pre_enable()
903 dev_info(&dsi->pdev->dev, "DSI regs before:\n"); in vc4_dsi_bridge_pre_enable()
904 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_bridge_pre_enable()
912 bridge->encoder); in vc4_dsi_bridge_pre_enable()
913 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; in vc4_dsi_bridge_pre_enable()
915 mode = &crtc_state->adjusted_mode; in vc4_dsi_bridge_pre_enable()
917 pixel_clock_hz = mode->clock * 1000; in vc4_dsi_bridge_pre_enable()
923 phy_clock = (pixel_clock_hz + 1000) * dsi->divider; in vc4_dsi_bridge_pre_enable()
924 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); in vc4_dsi_bridge_pre_enable()
926 dev_err(&dsi->pdev->dev, in vc4_dsi_bridge_pre_enable()
943 if (dsi->variant->port == 0) { in vc4_dsi_bridge_pre_enable()
947 if (dsi->lanes < 2) in vc4_dsi_bridge_pre_enable()
950 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) in vc4_dsi_bridge_pre_enable()
971 if (dsi->lanes < 4) in vc4_dsi_bridge_pre_enable()
973 if (dsi->lanes < 3) in vc4_dsi_bridge_pre_enable()
975 if (dsi->lanes < 2) in vc4_dsi_bridge_pre_enable()
988 ret = clk_prepare_enable(dsi->escape_clock); in vc4_dsi_bridge_pre_enable()
990 drm_err(bridge->dev, "Failed to turn on DSI escape clock: %d\n", in vc4_dsi_bridge_pre_enable()
995 ret = clk_prepare_enable(dsi->pll_phy_clock); in vc4_dsi_bridge_pre_enable()
997 drm_err(bridge->dev, "Failed to turn on DSI PLL: %d\n", ret); in vc4_dsi_bridge_pre_enable()
1001 hs_clock = clk_get_rate(dsi->pll_phy_clock); in vc4_dsi_bridge_pre_enable()
1011 ret = clk_set_rate(dsi->pixel_clock, dsip_clock); in vc4_dsi_bridge_pre_enable()
1017 ret = clk_prepare_enable(dsi->pixel_clock); in vc4_dsi_bridge_pre_enable()
1019 drm_err(bridge->dev, "Failed to turn on DSI pixel clock: %d\n", ret); in vc4_dsi_bridge_pre_enable()
1062 /* T_INIT is how long STOP is driven after power-up to in vc4_dsi_bridge_pre_enable()
1063 * indicate to the slave (also coming out of power-up) that in vc4_dsi_bridge_pre_enable()
1066 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and in vc4_dsi_bridge_pre_enable()
1087 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | in vc4_dsi_bridge_pre_enable()
1088 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | in vc4_dsi_bridge_pre_enable()
1089 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | in vc4_dsi_bridge_pre_enable()
1091 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? in vc4_dsi_bridge_pre_enable()
1093 (dsi->variant->port == 0 ? in vc4_dsi_bridge_pre_enable()
1094 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) : in vc4_dsi_bridge_pre_enable()
1095 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT))); in vc4_dsi_bridge_pre_enable()
1119 if (dsi->variant->port == 0) in vc4_dsi_bridge_pre_enable()
1131 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { in vc4_dsi_bridge_pre_enable()
1133 VC4_SET_FIELD(dsi->divider, in vc4_dsi_bridge_pre_enable()
1135 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | in vc4_dsi_bridge_pre_enable()
1157 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_bridge_enable()
1158 dev_info(&dsi->pdev->dev, "DSI regs after:\n"); in vc4_dsi_bridge_enable()
1159 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_bridge_enable()
1169 return drm_bridge_attach(bridge->encoder, dsi->out_bridge, in vc4_dsi_bridge_attach()
1170 &dsi->bridge, flags); in vc4_dsi_bridge_attach()
1177 struct drm_device *drm = dsi->bridge.dev; in vc4_dsi_host_transfer()
1181 bool is_long = mipi_dsi_packet_format_is_long(msg->type); in vc4_dsi_host_transfer()
1192 * The command FIFO takes byte-oriented data, but is of in vc4_dsi_host_transfer()
1206 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) / in vc4_dsi_host_transfer()
1215 if (msg->rx_len) { in vc4_dsi_host_transfer()
1235 if (msg->flags & MIPI_DSI_MSG_USE_LPM) in vc4_dsi_host_transfer()
1255 dsi->xfer_result = 0; in vc4_dsi_host_transfer()
1256 reinit_completion(&dsi->xfer_completion); in vc4_dsi_host_transfer()
1257 if (dsi->variant->port == 0) { in vc4_dsi_host_transfer()
1260 if (msg->rx_len) { in vc4_dsi_host_transfer()
1272 if (msg->rx_len) { in vc4_dsi_host_transfer()
1285 if (!wait_for_completion_timeout(&dsi->xfer_completion, in vc4_dsi_host_transfer()
1287 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); in vc4_dsi_host_transfer()
1288 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n", in vc4_dsi_host_transfer()
1290 ret = -ETIMEDOUT; in vc4_dsi_host_transfer()
1292 ret = dsi->xfer_result; in vc4_dsi_host_transfer()
1300 if (ret == 0 && msg->rx_len) { in vc4_dsi_host_transfer()
1302 u8 *msg_rx = msg->rx_buf; in vc4_dsi_host_transfer()
1308 if (rxlen != msg->rx_len) { in vc4_dsi_host_transfer()
1310 rxlen, (int)msg->rx_len); in vc4_dsi_host_transfer()
1311 ret = -ENXIO; in vc4_dsi_host_transfer()
1315 for (i = 0; i < msg->rx_len; i++) in vc4_dsi_host_transfer()
1322 if (msg->rx_len > 1) { in vc4_dsi_host_transfer()
1352 dsi->lanes = device->lanes; in vc4_dsi_host_attach()
1353 dsi->channel = device->channel; in vc4_dsi_host_attach()
1354 dsi->mode_flags = device->mode_flags; in vc4_dsi_host_attach()
1356 switch (device->format) { in vc4_dsi_host_attach()
1358 dsi->format = DSI_PFORMAT_RGB888; in vc4_dsi_host_attach()
1359 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1362 dsi->format = DSI_PFORMAT_RGB666; in vc4_dsi_host_attach()
1363 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1366 dsi->format = DSI_PFORMAT_RGB666_PACKED; in vc4_dsi_host_attach()
1367 dsi->divider = 18 / dsi->lanes; in vc4_dsi_host_attach()
1370 dsi->format = DSI_PFORMAT_RGB565; in vc4_dsi_host_attach()
1371 dsi->divider = 16 / dsi->lanes; in vc4_dsi_host_attach()
1374 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n", in vc4_dsi_host_attach()
1375 dsi->format); in vc4_dsi_host_attach()
1379 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { in vc4_dsi_host_attach()
1380 dev_err(&dsi->pdev->dev, in vc4_dsi_host_attach()
1385 drm_bridge_add(&dsi->bridge); in vc4_dsi_host_attach()
1387 ret = component_add(&dsi->pdev->dev, &vc4_dsi_ops); in vc4_dsi_host_attach()
1389 drm_bridge_remove(&dsi->bridge); in vc4_dsi_host_attach()
1401 component_del(&dsi->pdev->dev, &vc4_dsi_ops); in vc4_dsi_host_detach()
1402 drm_bridge_remove(&dsi->bridge); in vc4_dsi_host_detach()
1426 struct drm_device *drm = encoder->dev; in vc4_dsi_late_register()
1429 vc4_debugfs_add_regset32(drm, dsi->variant->debugfs_name, &dsi->regset); in vc4_dsi_late_register()
1461 { .compatible = "brcm,bcm2711-dsi1", &bcm2711_dsi1_variant },
1462 { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant },
1463 { .compatible = "brcm,bcm2835-dsi1", &bcm2835_dsi1_variant },
1474 drm_err(dsi->bridge.dev, "DSI%d: %s error\n", dsi->variant->port, in dsi_handle_error()
1525 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE : in vc4_dsi_irq_handler()
1528 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1531 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1532 dsi->xfer_result = -ETIMEDOUT; in vc4_dsi_irq_handler()
1540 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1541 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1547 struct device *dev = &dsi->pdev->dev; in vc4_dsi_init_phy_clocks()
1548 const char *parent_name = __clk_get_name(dsi->pll_phy_clock); in vc4_dsi_init_phy_clocks()
1559 dsi->clk_onecell = devm_kzalloc(dev, in vc4_dsi_init_phy_clocks()
1560 sizeof(*dsi->clk_onecell) + in vc4_dsi_init_phy_clocks()
1564 if (!dsi->clk_onecell) in vc4_dsi_init_phy_clocks()
1565 return -ENOMEM; in vc4_dsi_init_phy_clocks()
1566 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks); in vc4_dsi_init_phy_clocks()
1569 struct clk_fixed_factor *fix = &dsi->phy_clocks[i]; in vc4_dsi_init_phy_clocks()
1575 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name); in vc4_dsi_init_phy_clocks()
1586 fix->mult = 1; in vc4_dsi_init_phy_clocks()
1587 fix->div = phy_clocks[i].div; in vc4_dsi_init_phy_clocks()
1588 fix->hw.init = &init; in vc4_dsi_init_phy_clocks()
1596 ret = devm_clk_hw_register(dev, &fix->hw); in vc4_dsi_init_phy_clocks()
1600 dsi->clk_onecell->hws[i] = &fix->hw; in vc4_dsi_init_phy_clocks()
1603 return of_clk_add_hw_provider(dev->of_node, in vc4_dsi_init_phy_clocks()
1605 dsi->clk_onecell); in vc4_dsi_init_phy_clocks()
1611 struct device *dev = &dsi->pdev->dev; in vc4_dsi_dma_mem_release()
1613 dma_free_coherent(dev, 4, dsi->reg_dma_mem, dsi->reg_dma_paddr); in vc4_dsi_dma_mem_release()
1614 dsi->reg_dma_mem = NULL; in vc4_dsi_dma_mem_release()
1621 dma_release_channel(dsi->reg_dma_chan); in vc4_dsi_dma_chan_release()
1622 dsi->reg_dma_chan = NULL; in vc4_dsi_dma_chan_release()
1635 kref_get(&dsi->kref); in vc4_dsi_get()
1640 kref_put(&dsi->kref, &vc4_dsi_release); in vc4_dsi_put()
1655 struct drm_encoder *encoder = &dsi->encoder.base; in vc4_dsi_bind()
1664 dsi->variant = of_device_get_match_data(dev); in vc4_dsi_bind()
1666 dsi->encoder.type = dsi->variant->port ? in vc4_dsi_bind()
1669 dsi->regs = vc4_ioremap_regs(pdev, 0); in vc4_dsi_bind()
1670 if (IS_ERR(dsi->regs)) in vc4_dsi_bind()
1671 return PTR_ERR(dsi->regs); in vc4_dsi_bind()
1673 dsi->regset.base = dsi->regs; in vc4_dsi_bind()
1674 dsi->regset.regs = dsi->variant->regs; in vc4_dsi_bind()
1675 dsi->regset.nregs = dsi->variant->nregs; in vc4_dsi_bind()
1680 return -ENODEV; in vc4_dsi_bind()
1683 /* DSI1 on BCM2835/6/7 has a broken AXI slave that doesn't respond to in vc4_dsi_bind()
1687 if (dsi->variant->broken_axi_workaround) { in vc4_dsi_bind()
1690 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4, in vc4_dsi_bind()
1691 &dsi->reg_dma_paddr, in vc4_dsi_bind()
1693 if (!dsi->reg_dma_mem) { in vc4_dsi_bind()
1695 return -ENOMEM; in vc4_dsi_bind()
1705 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask); in vc4_dsi_bind()
1706 if (IS_ERR(dsi->reg_dma_chan)) { in vc4_dsi_bind()
1707 ret = PTR_ERR(dsi->reg_dma_chan); in vc4_dsi_bind()
1708 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1722 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node, in vc4_dsi_bind()
1726 init_completion(&dsi->xfer_completion); in vc4_dsi_bind()
1727 /* At startup enable error-reporting interrupts and nothing else. */ in vc4_dsi_bind()
1732 if (dsi->reg_dma_mem) in vc4_dsi_bind()
1742 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1747 dsi->escape_clock = devm_clk_get(dev, "escape"); in vc4_dsi_bind()
1748 if (IS_ERR(dsi->escape_clock)) { in vc4_dsi_bind()
1749 ret = PTR_ERR(dsi->escape_clock); in vc4_dsi_bind()
1750 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1755 dsi->pll_phy_clock = devm_clk_get(dev, "phy"); in vc4_dsi_bind()
1756 if (IS_ERR(dsi->pll_phy_clock)) { in vc4_dsi_bind()
1757 ret = PTR_ERR(dsi->pll_phy_clock); in vc4_dsi_bind()
1758 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1763 dsi->pixel_clock = devm_clk_get(dev, "pixel"); in vc4_dsi_bind()
1764 if (IS_ERR(dsi->pixel_clock)) { in vc4_dsi_bind()
1765 ret = PTR_ERR(dsi->pixel_clock); in vc4_dsi_bind()
1766 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1771 dsi->out_bridge = drmm_of_get_bridge(drm, dev->of_node, 0, 0); in vc4_dsi_bind()
1772 if (IS_ERR(dsi->out_bridge)) in vc4_dsi_bind()
1773 return PTR_ERR(dsi->out_bridge); in vc4_dsi_bind()
1776 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000); in vc4_dsi_bind()
1797 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0); in vc4_dsi_bind()
1810 struct device *dev = &pdev->dev; in vc4_dsi_dev_probe()
1815 return -ENOMEM; in vc4_dsi_dev_probe()
1818 kref_init(&dsi->kref); in vc4_dsi_dev_probe()
1820 dsi->pdev = pdev; in vc4_dsi_dev_probe()
1821 dsi->bridge.funcs = &vc4_dsi_bridge_funcs; in vc4_dsi_dev_probe()
1823 dsi->bridge.of_node = dev->of_node; in vc4_dsi_dev_probe()
1825 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; in vc4_dsi_dev_probe()
1826 dsi->dsi_host.ops = &vc4_dsi_host_ops; in vc4_dsi_dev_probe()
1827 dsi->dsi_host.dev = dev; in vc4_dsi_dev_probe()
1828 mipi_dsi_host_register(&dsi->dsi_host); in vc4_dsi_dev_probe()
1835 struct device *dev = &pdev->dev; in vc4_dsi_dev_remove()
1838 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_dev_remove()