54 #define CRTC_WRITE(offset, val)								\  macro
316 	CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);  in vc4_crtc_pixelvalve_reset()
317 	CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);  in vc4_crtc_pixelvalve_reset()
362 	CRTC_WRITE(PV_HORZA,  in vc4_crtc_config_pv()
368 	CRTC_WRITE(PV_HORZB,  in vc4_crtc_config_pv()
394 		CRTC_WRITE(PV_VERTA_EVEN,  in vc4_crtc_config_pv()
397 		CRTC_WRITE(PV_VERTB_EVEN,  in vc4_crtc_config_pv()
404 		CRTC_WRITE(PV_V_CONTROL,  in vc4_crtc_config_pv()
412 		CRTC_WRITE(PV_VSYNCD_EVEN,  in vc4_crtc_config_pv()
415 		CRTC_WRITE(PV_V_CONTROL,  in vc4_crtc_config_pv()
418 		CRTC_WRITE(PV_VSYNCD_EVEN, 0);  in vc4_crtc_config_pv()
421 	CRTC_WRITE(PV_VERTA,  in vc4_crtc_config_pv()
424 	CRTC_WRITE(PV_VERTB,  in vc4_crtc_config_pv()
429 		CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);  in vc4_crtc_config_pv()
432 		CRTC_WRITE(PV_MUX_CFG,  in vc4_crtc_config_pv()
436 	CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |  in vc4_crtc_config_pv()
479 	CRTC_WRITE(PV_V_CONTROL,  in vc4_crtc_disable()
644 	CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);  in vc4_crtc_atomic_enable()
652 	CRTC_WRITE(PV_V_CONTROL,  in vc4_crtc_atomic_enable()
757 	CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);  in vc4_enable_vblank()
773 	CRTC_WRITE(PV_INTEN, 0);  in vc4_disable_vblank()
822 		CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);  in vc4_crtc_irq_handler()
1419 	CRTC_WRITE(PV_INTEN, 0);  in vc4_crtc_bind()
1420 	CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);  in vc4_crtc_bind()
1439 	CRTC_WRITE(PV_INTEN, 0);  in vc4_crtc_unbind()