Lines Matching full:total
26 {"QPU", "QPU-total-idle-clk-cycles", "[QPU] Total idle clock cycles for all QPUs"},
27 …{"QPU", "QPU-total-active-clk-cycles-vertex-coord-shading", "[QPU] Total active clock cycles for a…
28 …{"QPU", "QPU-total-active-clk-cycles-fragment-shading", "[QPU] Total active clock cycles for all Q…
29 …{"QPU", "QPU-total-clk-cycles-executing-valid-instr", "[QPU] Total clock cycles for all QPUs execu…
30 …{"QPU", "QPU-total-clk-cycles-waiting-TMU", "[QPU] Total clock cycles for all QPUs stalled waiting…
31 …{"QPU", "QPU-total-clk-cycles-waiting-scoreboard", "[QPU] Total clock cycles for all QPUs stalled …
32 …{"QPU", "QPU-total-clk-cycles-waiting-varyings", "[QPU] Total clock cycles for all QPUs stalled wa…
33 {"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"},
34 {"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"},
35 {"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"},
36 {"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"},
37 {"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
38 …{"TMU", "TMU-total-text-cache-miss", "[TMU] Total texture cache misses (number of fetches from mem…
39 …{"VPM", "VPM-total-clk-cycles-VDW-stalled", "[VPM] Total clock cycles VDW is stalled waiting for V…
40 …{"VPM", "VPM-total-clk-cycles-VCD-stalled", "[VPM] Total clock cycles VCD is stalled waiting for V…
43 {"L2T", "L2T-total-cache-hit", "[L2T] Total Level 2 cache hits"},
44 {"L2T", "L2T-total-cache-miss", "[L2T] Total Level 2 cache misses"},
46 …{"QPU", "QPU-total-clk-cycles-waiting-vertex-coord-shading", "[QPU] Total stalled clock cycles for…
47 …{"QPU", "QPU-total-clk-cycles-waiting-fragment-shading", "[QPU] Total stalled clock cycles for all…
48 {"PTB", "PTB-primitives-binned", "[PTB] Total primitives binned"},
53 {"AXI", "AXI-write-bytes-seen-watch-0", "[AXI] Total bytes written seen by watch 0"},
54 {"AXI", "AXI-read-bytes-seen-watch-0", "[AXI] Total bytes read seen by watch 0"},
59 {"AXI", "AXI-write-bytes-seen-watch-1", "[AXI] Total bytes written seen by watch 1"},
60 {"AXI", "AXI-read-bytes-seen-watch-1", "[AXI] Total bytes read seen by watch 1"},
62 {"TMU", "TMU-total-config-access", "[TMU] Total config accesses"},
84 {"CORE", "core-memory-writes", "[CORE] Total memory writes"},
85 {"L2T", "L2T-memory-writes", "[L2T] Total memory writes"},
86 {"PTB", "PTB-memory-writes", "[PTB] Total memory writes"},
87 {"TLB", "TLB-memory-writes", "[TLB] Total memory writes"},
88 {"CORE", "core-memory-reads", "[CORE] Total memory reads"},
89 {"L2T", "L2T-memory-reads", "[L2T] Total memory reads"},
90 {"PTB", "PTB-memory-reads", "[PTB] Total memory reads"},
91 {"PSE", "PSE-memory-reads", "[PSE] Total memory reads"},
92 {"TLB", "TLB-memory-reads", "[TLB] Total memory reads"},
93 {"GMP", "GMP-memory-reads", "[GMP] Total memory reads"},
94 {"PTB", "PTB-memory-words-writes", "[PTB] Total memory words written"},
95 {"TLB", "TLB-memory-words-writes", "[TLB] Total memory words written"},
96 {"PSE", "PSE-memory-words-reads", "[PSE] Total memory words read"},
97 {"TLB", "TLB-memory-words-reads", "[TLB] Total memory words read"},
98 {"TMU", "TMU-MRU-hits", "[TMU] Total MRU hits"},
119 {"PTB", "PTB-primitives-binned", "[PTB] Total primitives binned"},
121 {"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"},
122 {"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"},
123 {"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"},
124 {"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"},
127 {"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
130 {"TMU", "TMU-total-text-quads-x4-access", "[TMU] Total texture cache x4 access"},
131 {"L2T", "L2T-total-cache-hit", "[L2T] Total Level 2 cache hits"},
132 {"L2T", "L2T-total-cache-miss", "[L2T] Total Level 2 cache misses"},
157 {"AXI", "AXI-write-bytes-seen-watch-0", "[AXI] Total bytes written seen by watch 0"},
158 {"AXI", "AXI-read-bytes-seen-watch-0", "[AXI] Total bytes read seen by watch 0"},
163 {"AXI", "AXI-write-bytes-seen-watch-1", "[AXI] Total bytes written seen by watch 1"},
164 {"AXI", "AXI-read-bytes-seen-watch-1", "[AXI] Total bytes read seen by watch 1"},
165 {"CORE", "core-memory-writes", "[CORE] Total memory writes"},
166 {"L2T", "L2T-memory-writes", "[L2T] Total memory writes"},
167 {"PTB", "PTB-memory-writes", "[PTB] Total memory writes"},
168 {"TLB", "TLB-memory-writes", "[TLB] Total memory writes"},
169 {"CORE", "core-memory-reads", "[CORE] Total memory reads"},
170 {"L2T", "L2T-memory-reads", "[L2T] Total memory reads"},
171 {"PTB", "PTB-memory-reads", "[PTB] Total memory reads"},
172 {"PSE", "PSE-memory-reads", "[PSE] Total memory reads"},
173 {"TLB", "TLB-memory-reads", "[TLB] Total memory reads"},
174 {"PTB", "PTB-memory-words-writes", "[PTB] Total memory words written"},
175 {"TLB", "TLB-memory-words-writes", "[TLB] Total memory words written"},
176 {"PSE", "PSE-memory-words-reads", "[PSE] Total memory words read"},
177 {"TLB", "TLB-memory-words-reads", "[TLB] Total memory words read"},
180 {"AXI", "AXI-read-wait-cycles", "[AXI] Read total wait cycles"},
181 {"AXI", "AXI-write-wait-cycles", "[AXI] Write total wait cycles"},
187 …{"QPU", "QPU-total-active-clk-cycles-fragment-shading", "[QPU] Total active clock cycles for all Q…
189 …{"QPU", "QPU-total-clk-cycles-waiting-fragment-shading", "[QPU] Total stalled clock cycles for all…