101 	/* Short representation (e.g. 33, 41) of the V3D tech version */
104 	/* Short representation (e.g. 5, 6) of the V3D tech revision */
128 	/* virtual address bits from V3D to the MMU. */
131 	/* Number of V3D cores. */
191 v3d_has_csd(struct v3d_dev *v3d)  in v3d_has_csd()  argument
193 	return v3d->ver >= 41;  in v3d_has_csd()
196 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)  argument
200 	struct v3d_dev *v3d;  member
235 	/* v3d seqno for signaled() test */
246 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
247 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
249 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
250 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
252 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
253 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
255 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
256 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
263 	struct v3d_dev *v3d;  member
271 	/* v3d fence to be signaled by IRQ handler when the job is complete. */
528 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
533 void v3d_reset(struct v3d_dev *v3d);
534 void v3d_invalidate_caches(struct v3d_dev *v3d);
535 void v3d_clean_caches(struct v3d_dev *v3d);
550 int v3d_irq_init(struct v3d_dev *v3d);
551 void v3d_irq_enable(struct v3d_dev *v3d);
552 void v3d_irq_disable(struct v3d_dev *v3d);
553 void v3d_irq_reset(struct v3d_dev *v3d);
556 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
566 int v3d_sched_init(struct v3d_dev *v3d);
567 void v3d_sched_fini(struct v3d_dev *v3d);
570 void v3d_perfmon_init(struct v3d_dev *v3d);
573 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon);
574 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon,