drm/tve200/tve200_drm.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
6  * Copyright (C) 2006-2008 Intel Corporation
28 /* Bits 2-31 are valid physical base addresses */
36 #define TVE200_INT_BUS_ERR		BIT(7)
37 #define TVE200_INT_V_STATUS		BIT(6) /* vertical blank */
38 #define TVE200_INT_V_NEXT_FRAME		BIT(5)
39 #define TVE200_INT_U_NEXT_FRAME		BIT(4)
40 #define TVE200_INT_Y_NEXT_FRAME		BIT(3)
41 #define TVE200_INT_V_FIFO_UNDERRUN	BIT(2)
42 #define TVE200_INT_U_FIFO_UNDERRUN	BIT(1)
43 #define TVE200_INT_Y_FIFO_UNDERRUN	BIT(0)
49 #define TVE200_CTRL_YUV420		BIT(31)
50 #define TVE200_CTRL_CSMODE		BIT(30)
51 #define TVE200_CTRL_NONINTERLACE	BIT(28) /* 0 = non-interlace CCIR656 */
52 #define TVE200_CTRL_TVCLKP		BIT(27) /* Inverted clock phase */
68 #define TVE200_CTRL_BBBP		BIT(15) /* 0 = little-endian */
69 /* Bits 12..14 define the YCbCr ordering */
70 #define TVE200_CTRL_YCBCRODR_CB0Y0CR0Y1	(0 << 12)
71 #define TVE200_CTRL_YCBCRODR_Y0CB0Y1CR0	(1 << 12)
72 #define TVE200_CTRL_YCBCRODR_CR0Y0CB0Y1	(2 << 12)
73 #define TVE200_CTRL_YCBCRODR_Y1CB0Y0CR0	(3 << 12)
74 #define TVE200_CTRL_YCBCRODR_CR0Y1CB0Y0	(4 << 12)
75 #define TVE200_CTRL_YCBCRODR_Y1CR0Y0CB0	(5 << 12)
76 #define TVE200_CTRL_YCBCRODR_CB0Y1CR0Y0	(6 << 12)
77 #define TVE200_CTRL_YCBCRODR_Y0CR0Y1CB0	(7 << 12)
82 #define TVE200_CTRL_NTSC		BIT(9) /* 0 = PAL, 1 = NTSC */
83 #define TVE200_CTRL_INTERLACE		BIT(8) /* 1 = interlace, only for D1 */
94 #define TVE200_VSTSTYPE_BITS		(BIT(4) | BIT(5))
95 #define TVE200_BGR			BIT(1) /* 0 = RGB, 1 = BGR */
96 #define TVE200_TVEEN			BIT(0) /* Enable TVE block */
102 #define TVE200_CTRL_4_RESET		BIT(0) /* triggers reset of TVE200 */