Lines Matching +full:mode +full:- +full:reg

1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
65 struct drm_device *dev = crtc->dev; in set_scanout()
66 struct tilcdc_drm_private *priv = dev->dev_private; in set_scanout()
73 start = gem->dma_addr + fb->offsets[0] + in set_scanout()
74 crtc->y * fb->pitches[0] + in set_scanout()
75 crtc->x * fb->format->cpp[0]; in set_scanout()
77 end = start + (crtc->mode.vdisplay * fb->pitches[0]); in set_scanout()
84 if (priv->rev == 1) in set_scanout()
85 end -= 1; in set_scanout()
94 * should still be loaded. The first 16-bit entry must be 0x4000 while
100 struct drm_device *dev = crtc->dev; in tilcdc_crtc_load_palette()
101 struct tilcdc_drm_private *priv = dev->dev_private; in tilcdc_crtc_load_palette()
104 reinit_completion(&tilcdc_crtc->palette_loaded); in tilcdc_crtc_load_palette()
108 tilcdc_crtc->palette_dma_handle); in tilcdc_crtc_load_palette()
110 (u32) tilcdc_crtc->palette_dma_handle + in tilcdc_crtc_load_palette()
111 TILCDC_PALETTE_SIZE - 1); in tilcdc_crtc_load_palette()
113 /* Set dma load mode for palette loading only. */ in tilcdc_crtc_load_palette()
119 if (priv->rev == 1) in tilcdc_crtc_load_palette()
128 ret = wait_for_completion_timeout(&tilcdc_crtc->palette_loaded, in tilcdc_crtc_load_palette()
131 dev_err(dev->dev, "%s: Palette loading timeout", __func__); in tilcdc_crtc_load_palette()
135 if (priv->rev == 1) in tilcdc_crtc_load_palette()
143 struct tilcdc_drm_private *priv = dev->dev_private; in tilcdc_crtc_enable_irqs()
147 if (priv->rev == 1) { in tilcdc_crtc_enable_irqs()
160 struct tilcdc_drm_private *priv = dev->dev_private; in tilcdc_crtc_disable_irqs()
163 if (priv->rev == 1) { in tilcdc_crtc_disable_irqs()
179 struct drm_device *dev = crtc->dev; in reset()
180 struct tilcdc_drm_private *priv = dev->dev_private; in reset()
182 if (priv->rev != 2) in reset()
199 return (unsigned int)(abs(((rr - r) * 100) / r)); in tilcdc_pclk_diff()
204 struct drm_device *dev = crtc->dev; in tilcdc_crtc_set_clk()
205 struct tilcdc_drm_private *priv = dev->dev_private; in tilcdc_crtc_set_clk()
213 /* mode.clock is in KHz, set_rate wants parameter in Hz */ in tilcdc_crtc_set_clk()
214 pclk_rate = crtc->mode.clock * 1000; in tilcdc_crtc_set_clk()
216 ret = clk_set_rate(priv->clk, pclk_rate * clkdiv); in tilcdc_crtc_set_clk()
217 clk_rate = clk_get_rate(priv->clk); in tilcdc_crtc_set_clk()
229 dev_err(dev->dev, in tilcdc_crtc_set_clk()
230 "failed to set the pixel clock - unable to read current lcdc clock rate\n"); in tilcdc_crtc_set_clk()
240 * 5% is an arbitrary value - LCDs are usually quite tolerant in tilcdc_crtc_set_clk()
246 dev_warn(dev->dev, in tilcdc_crtc_set_clk()
252 tilcdc_crtc->lcd_fck_rate = clk_rate; in tilcdc_crtc_set_clk()
254 DBG("lcd_clk=%u, mode clock=%d, div=%u", in tilcdc_crtc_set_clk()
255 tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv); in tilcdc_crtc_set_clk()
261 if (priv->rev == 2) in tilcdc_crtc_set_clk()
267 static uint tilcdc_mode_hvtotal(const struct drm_display_mode *mode) in tilcdc_mode_hvtotal() argument
269 return (uint) div_u64(1000llu * mode->htotal * mode->vtotal, in tilcdc_mode_hvtotal()
270 mode->clock); in tilcdc_mode_hvtotal()
276 struct drm_device *dev = crtc->dev; in tilcdc_crtc_set_mode()
277 struct tilcdc_drm_private *priv = dev->dev_private; in tilcdc_crtc_set_mode()
278 const struct tilcdc_panel_info *info = tilcdc_crtc->info; in tilcdc_crtc_set_mode()
279 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; in tilcdc_crtc_set_mode() local
280 struct drm_display_mode *mode = &crtc->state->adjusted_mode; in tilcdc_crtc_set_mode() local
281 struct drm_framebuffer *fb = crtc->primary->state->fb; in tilcdc_crtc_set_mode()
290 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; in tilcdc_crtc_set_mode()
291 switch (info->dma_burst_sz) { in tilcdc_crtc_set_mode()
293 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); in tilcdc_crtc_set_mode()
296 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); in tilcdc_crtc_set_mode()
299 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); in tilcdc_crtc_set_mode()
302 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); in tilcdc_crtc_set_mode()
305 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); in tilcdc_crtc_set_mode()
308 dev_err(dev->dev, "invalid burst size\n"); in tilcdc_crtc_set_mode()
311 reg |= (info->fifo_th << 8); in tilcdc_crtc_set_mode()
312 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); in tilcdc_crtc_set_mode()
315 hbp = mode->htotal - mode->hsync_end; in tilcdc_crtc_set_mode()
316 hfp = mode->hsync_start - mode->hdisplay; in tilcdc_crtc_set_mode()
317 hsw = mode->hsync_end - mode->hsync_start; in tilcdc_crtc_set_mode()
318 vbp = mode->vtotal - mode->vsync_end; in tilcdc_crtc_set_mode()
319 vfp = mode->vsync_start - mode->vdisplay; in tilcdc_crtc_set_mode()
320 vsw = mode->vsync_end - mode->vsync_start; in tilcdc_crtc_set_mode()
323 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); in tilcdc_crtc_set_mode()
326 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; in tilcdc_crtc_set_mode()
327 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | in tilcdc_crtc_set_mode()
328 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); in tilcdc_crtc_set_mode()
334 if (priv->rev == 2) { in tilcdc_crtc_set_mode()
336 reg &= ~0x78000033; in tilcdc_crtc_set_mode()
337 reg |= ((hfp-1) & 0x300) >> 8; in tilcdc_crtc_set_mode()
338 reg |= ((hbp-1) & 0x300) >> 4; in tilcdc_crtc_set_mode()
339 reg |= ((hsw-1) & 0x3c0) << 21; in tilcdc_crtc_set_mode()
341 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); in tilcdc_crtc_set_mode()
343 reg = (((mode->hdisplay >> 4) - 1) << 4) | in tilcdc_crtc_set_mode()
344 (((hbp-1) & 0xff) << 24) | in tilcdc_crtc_set_mode()
345 (((hfp-1) & 0xff) << 16) | in tilcdc_crtc_set_mode()
346 (((hsw-1) & 0x3f) << 10); in tilcdc_crtc_set_mode()
347 if (priv->rev == 2) in tilcdc_crtc_set_mode()
348 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; in tilcdc_crtc_set_mode()
349 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); in tilcdc_crtc_set_mode()
351 reg = ((mode->vdisplay - 1) & 0x3ff) | in tilcdc_crtc_set_mode()
354 (((vsw-1) & 0x3f) << 10); in tilcdc_crtc_set_mode()
355 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); in tilcdc_crtc_set_mode()
362 if (priv->rev == 2) { in tilcdc_crtc_set_mode()
363 if ((mode->vdisplay - 1) & 0x400) { in tilcdc_crtc_set_mode()
373 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & in tilcdc_crtc_set_mode()
377 reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ in tilcdc_crtc_set_mode()
378 if (info->tft_alt_mode) in tilcdc_crtc_set_mode()
379 reg |= LCDC_TFT_ALT_ENABLE; in tilcdc_crtc_set_mode()
380 if (priv->rev == 2) { in tilcdc_crtc_set_mode()
381 switch (fb->format->format) { in tilcdc_crtc_set_mode()
387 reg |= LCDC_V2_TFT_24BPP_UNPACK; in tilcdc_crtc_set_mode()
391 reg |= LCDC_V2_TFT_24BPP_MODE; in tilcdc_crtc_set_mode()
394 dev_err(dev->dev, "invalid pixel format\n"); in tilcdc_crtc_set_mode()
398 reg |= info->fdd << 12; in tilcdc_crtc_set_mode()
399 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); in tilcdc_crtc_set_mode()
401 if (info->invert_pxl_clk) in tilcdc_crtc_set_mode()
406 if (info->sync_ctrl) in tilcdc_crtc_set_mode()
411 if (info->sync_edge) in tilcdc_crtc_set_mode()
416 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tilcdc_crtc_set_mode()
421 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tilcdc_crtc_set_mode()
426 if (info->raster_order) in tilcdc_crtc_set_mode()
437 drm_mode_copy(&crtc->hwmode, &crtc->state->adjusted_mode); in tilcdc_crtc_set_mode()
439 tilcdc_crtc->hvtotal_us = in tilcdc_crtc_set_mode()
440 tilcdc_mode_hvtotal(&crtc->hwmode); in tilcdc_crtc_set_mode()
445 struct drm_device *dev = crtc->dev; in tilcdc_crtc_enable()
449 mutex_lock(&tilcdc_crtc->enable_lock); in tilcdc_crtc_enable()
450 if (tilcdc_crtc->enabled || tilcdc_crtc->shutdown) { in tilcdc_crtc_enable()
451 mutex_unlock(&tilcdc_crtc->enable_lock); in tilcdc_crtc_enable()
455 pm_runtime_get_sync(dev->dev); in tilcdc_crtc_enable()
469 * is taken before the raster DMA is started. The spin-lock is in tilcdc_crtc_enable()
470 * taken to have a memory barrier after taking the time-stamp in tilcdc_crtc_enable()
474 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); in tilcdc_crtc_enable()
475 tilcdc_crtc->last_vblank = ktime_get(); in tilcdc_crtc_enable()
477 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); in tilcdc_crtc_enable()
481 tilcdc_crtc->enabled = true; in tilcdc_crtc_enable()
482 mutex_unlock(&tilcdc_crtc->enable_lock); in tilcdc_crtc_enable()
494 struct drm_device *dev = crtc->dev; in tilcdc_crtc_off()
497 mutex_lock(&tilcdc_crtc->enable_lock); in tilcdc_crtc_off()
499 tilcdc_crtc->shutdown = true; in tilcdc_crtc_off()
500 if (!tilcdc_crtc->enabled) { in tilcdc_crtc_off()
501 mutex_unlock(&tilcdc_crtc->enable_lock); in tilcdc_crtc_off()
504 tilcdc_crtc->frame_done = false; in tilcdc_crtc_off()
511 ret = wait_event_timeout(tilcdc_crtc->frame_done_wq, in tilcdc_crtc_off()
512 tilcdc_crtc->frame_done, in tilcdc_crtc_off()
515 dev_err(dev->dev, "%s: timeout waiting for framedone\n", in tilcdc_crtc_off()
520 spin_lock_irq(&crtc->dev->event_lock); in tilcdc_crtc_off()
522 if (crtc->state->event) { in tilcdc_crtc_off()
523 drm_crtc_send_vblank_event(crtc, crtc->state->event); in tilcdc_crtc_off()
524 crtc->state->event = NULL; in tilcdc_crtc_off()
527 spin_unlock_irq(&crtc->dev->event_lock); in tilcdc_crtc_off()
531 pm_runtime_put_sync(dev->dev); in tilcdc_crtc_off()
533 tilcdc_crtc->enabled = false; in tilcdc_crtc_off()
534 mutex_unlock(&tilcdc_crtc->enable_lock); in tilcdc_crtc_off()
551 if (!crtc->state->event) in tilcdc_crtc_atomic_flush()
554 spin_lock_irq(&crtc->dev->event_lock); in tilcdc_crtc_atomic_flush()
555 drm_crtc_send_vblank_event(crtc, crtc->state->event); in tilcdc_crtc_atomic_flush()
556 crtc->state->event = NULL; in tilcdc_crtc_atomic_flush()
557 spin_unlock_irq(&crtc->dev->event_lock); in tilcdc_crtc_atomic_flush()
567 return crtc->state && crtc->state->enable && crtc->state->active; in tilcdc_crtc_is_on()
574 struct drm_crtc *crtc = &tilcdc_crtc->base; in tilcdc_crtc_recover_work()
576 dev_info(crtc->dev->dev, "%s: Reset CRTC", __func__); in tilcdc_crtc_recover_work()
578 drm_modeset_lock(&crtc->mutex, NULL); in tilcdc_crtc_recover_work()
586 drm_modeset_unlock(&crtc->mutex); in tilcdc_crtc_recover_work()
591 struct tilcdc_drm_private *priv = crtc->dev->dev_private; in tilcdc_crtc_destroy()
595 flush_workqueue(priv->wq); in tilcdc_crtc_destroy()
597 of_node_put(crtc->port); in tilcdc_crtc_destroy()
606 struct drm_device *dev = crtc->dev; in tilcdc_crtc_update_fb()
608 if (tilcdc_crtc->event) { in tilcdc_crtc_update_fb()
609 dev_err(dev->dev, "already pending page flip!\n"); in tilcdc_crtc_update_fb()
610 return -EBUSY; in tilcdc_crtc_update_fb()
613 tilcdc_crtc->event = event; in tilcdc_crtc_update_fb()
615 mutex_lock(&tilcdc_crtc->enable_lock); in tilcdc_crtc_update_fb()
617 if (tilcdc_crtc->enabled) { in tilcdc_crtc_update_fb()
622 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); in tilcdc_crtc_update_fb()
624 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank, in tilcdc_crtc_update_fb()
625 tilcdc_crtc->hvtotal_us); in tilcdc_crtc_update_fb()
629 tilcdc_crtc->next_fb = fb; in tilcdc_crtc_update_fb()
633 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); in tilcdc_crtc_update_fb()
636 mutex_unlock(&tilcdc_crtc->enable_lock); in tilcdc_crtc_update_fb()
642 const struct drm_display_mode *mode, in tilcdc_crtc_mode_fixup() argument
647 if (!tilcdc_crtc->simulate_vesa_sync) in tilcdc_crtc_mode_fixup()
651 * tilcdc does not generate VESA-compliant sync but aligns in tilcdc_crtc_mode_fixup()
656 adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; in tilcdc_crtc_mode_fixup()
657 adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW; in tilcdc_crtc_mode_fixup()
659 if (mode->flags & DRM_MODE_FLAG_NHSYNC) { in tilcdc_crtc_mode_fixup()
660 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; in tilcdc_crtc_mode_fixup()
661 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC; in tilcdc_crtc_mode_fixup()
663 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC; in tilcdc_crtc_mode_fixup()
664 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC; in tilcdc_crtc_mode_fixup()
676 if (!crtc_state->active) in tilcdc_crtc_atomic_check()
679 if (state->planes[0].ptr != crtc->primary || in tilcdc_crtc_atomic_check()
680 state->planes[0].state == NULL || in tilcdc_crtc_atomic_check()
681 state->planes[0].state->crtc != crtc) { in tilcdc_crtc_atomic_check()
682 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present"); in tilcdc_crtc_atomic_check()
683 return -EINVAL; in tilcdc_crtc_atomic_check()
692 struct drm_device *dev = crtc->dev; in tilcdc_crtc_enable_vblank()
693 struct tilcdc_drm_private *priv = dev->dev_private; in tilcdc_crtc_enable_vblank()
696 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); in tilcdc_crtc_enable_vblank()
700 if (priv->rev == 1) in tilcdc_crtc_enable_vblank()
707 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); in tilcdc_crtc_enable_vblank()
715 struct drm_device *dev = crtc->dev; in tilcdc_crtc_disable_vblank()
716 struct tilcdc_drm_private *priv = dev->dev_private; in tilcdc_crtc_disable_vblank()
719 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); in tilcdc_crtc_disable_vblank()
721 if (priv->rev == 1) in tilcdc_crtc_disable_vblank()
728 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); in tilcdc_crtc_disable_vblank()
734 struct drm_device *dev = crtc->dev; in tilcdc_crtc_reset()
740 pm_runtime_get_sync(dev->dev); in tilcdc_crtc_reset()
746 tilcdc_crtc->frame_done = false; in tilcdc_crtc_reset()
749 ret = wait_event_timeout(tilcdc_crtc->frame_done_wq, in tilcdc_crtc_reset()
750 tilcdc_crtc->frame_done, in tilcdc_crtc_reset()
753 dev_err(dev->dev, "%s: timeout waiting for framedone\n", in tilcdc_crtc_reset()
756 pm_runtime_put_sync(dev->dev); in tilcdc_crtc_reset()
772 const struct drm_display_mode *mode) in tilcdc_crtc_mode_valid() argument
774 struct tilcdc_drm_private *priv = crtc->dev->dev_private; in tilcdc_crtc_mode_valid()
782 if (mode->hdisplay > priv->max_width) in tilcdc_crtc_mode_valid()
786 if (mode->hdisplay & 0xf) in tilcdc_crtc_mode_valid()
789 if (mode->vdisplay > 2048) in tilcdc_crtc_mode_valid()
792 DBG("Processing mode %dx%d@%d with pixel clock %d", in tilcdc_crtc_mode_valid()
793 mode->hdisplay, mode->vdisplay, in tilcdc_crtc_mode_valid()
794 drm_mode_vrefresh(mode), mode->clock); in tilcdc_crtc_mode_valid()
796 hbp = mode->htotal - mode->hsync_end; in tilcdc_crtc_mode_valid()
797 hfp = mode->hsync_start - mode->hdisplay; in tilcdc_crtc_mode_valid()
798 hsw = mode->hsync_end - mode->hsync_start; in tilcdc_crtc_mode_valid()
799 vbp = mode->vtotal - mode->vsync_end; in tilcdc_crtc_mode_valid()
800 vfp = mode->vsync_start - mode->vdisplay; in tilcdc_crtc_mode_valid()
801 vsw = mode->vsync_end - mode->vsync_start; in tilcdc_crtc_mode_valid()
803 if ((hbp-1) & ~0x3ff) { in tilcdc_crtc_mode_valid()
804 DBG("Pruning mode: Horizontal Back Porch out of range"); in tilcdc_crtc_mode_valid()
808 if ((hfp-1) & ~0x3ff) { in tilcdc_crtc_mode_valid()
809 DBG("Pruning mode: Horizontal Front Porch out of range"); in tilcdc_crtc_mode_valid()
813 if ((hsw-1) & ~0x3ff) { in tilcdc_crtc_mode_valid()
814 DBG("Pruning mode: Horizontal Sync Width out of range"); in tilcdc_crtc_mode_valid()
819 DBG("Pruning mode: Vertical Back Porch out of range"); in tilcdc_crtc_mode_valid()
824 DBG("Pruning mode: Vertical Front Porch out of range"); in tilcdc_crtc_mode_valid()
828 if ((vsw-1) & ~0x3f) { in tilcdc_crtc_mode_valid()
829 DBG("Pruning mode: Vertical Sync Width out of range"); in tilcdc_crtc_mode_valid()
837 if (mode->clock > priv->max_pixelclock) { in tilcdc_crtc_mode_valid()
838 DBG("Pruning mode: pixel clock too high"); in tilcdc_crtc_mode_valid()
846 if (mode->hdisplay > priv->max_width) in tilcdc_crtc_mode_valid()
850 bandwidth = mode->hdisplay * mode->vdisplay * in tilcdc_crtc_mode_valid()
851 drm_mode_vrefresh(mode); in tilcdc_crtc_mode_valid()
852 if (bandwidth > priv->max_bandwidth) { in tilcdc_crtc_mode_valid()
853 DBG("Pruning mode: exceeds defined bandwidth limit"); in tilcdc_crtc_mode_valid()
873 tilcdc_crtc->info = info; in tilcdc_crtc_set_panel_info()
881 tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync; in tilcdc_crtc_set_simulate_vesa_sync()
886 struct drm_device *dev = crtc->dev; in tilcdc_crtc_update_clk()
887 struct tilcdc_drm_private *priv = dev->dev_private; in tilcdc_crtc_update_clk()
890 drm_modeset_lock(&crtc->mutex, NULL); in tilcdc_crtc_update_clk()
891 if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) { in tilcdc_crtc_update_clk()
893 pm_runtime_get_sync(dev->dev); in tilcdc_crtc_update_clk()
899 pm_runtime_put_sync(dev->dev); in tilcdc_crtc_update_clk()
902 drm_modeset_unlock(&crtc->mutex); in tilcdc_crtc_update_clk()
910 struct drm_device *dev = crtc->dev; in tilcdc_crtc_irq()
911 struct tilcdc_drm_private *priv = dev->dev_private; in tilcdc_crtc_irq()
912 uint32_t stat, reg; in tilcdc_crtc_irq() local
923 spin_lock(&tilcdc_crtc->irq_lock); in tilcdc_crtc_irq()
925 tilcdc_crtc->last_vblank = now; in tilcdc_crtc_irq()
927 if (tilcdc_crtc->next_fb) { in tilcdc_crtc_irq()
928 set_scanout(crtc, tilcdc_crtc->next_fb); in tilcdc_crtc_irq()
929 tilcdc_crtc->next_fb = NULL; in tilcdc_crtc_irq()
933 spin_unlock(&tilcdc_crtc->irq_lock); in tilcdc_crtc_irq()
940 spin_lock(&dev->event_lock); in tilcdc_crtc_irq()
942 event = tilcdc_crtc->event; in tilcdc_crtc_irq()
943 tilcdc_crtc->event = NULL; in tilcdc_crtc_irq()
947 spin_unlock(&dev->event_lock); in tilcdc_crtc_irq()
950 if (tilcdc_crtc->frame_intact) in tilcdc_crtc_irq()
951 tilcdc_crtc->sync_lost_count = 0; in tilcdc_crtc_irq()
953 tilcdc_crtc->frame_intact = true; in tilcdc_crtc_irq()
957 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow", in tilcdc_crtc_irq()
961 complete(&tilcdc_crtc->palette_loaded); in tilcdc_crtc_irq()
962 if (priv->rev == 1) in tilcdc_crtc_irq()
971 dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost", in tilcdc_crtc_irq()
973 tilcdc_crtc->frame_intact = false; in tilcdc_crtc_irq()
974 if (priv->rev == 1) { in tilcdc_crtc_irq()
975 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG); in tilcdc_crtc_irq()
976 if (reg & LCDC_RASTER_ENABLE) { in tilcdc_crtc_irq()
983 if (tilcdc_crtc->sync_lost_count++ > in tilcdc_crtc_irq()
985 dev_err(dev->dev, in tilcdc_crtc_irq()
989 &tilcdc_crtc->recover_work); in tilcdc_crtc_irq()
992 tilcdc_crtc->sync_lost_count = 0; in tilcdc_crtc_irq()
998 tilcdc_crtc->frame_done = true; in tilcdc_crtc_irq()
999 wake_up(&tilcdc_crtc->frame_done_wq); in tilcdc_crtc_irq()
1001 if (priv->rev == 1) in tilcdc_crtc_irq()
1007 if (priv->rev == 2) { in tilcdc_crtc_irq()
1019 struct tilcdc_drm_private *priv = dev->dev_private; in tilcdc_crtc_create()
1024 tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL); in tilcdc_crtc_create()
1026 return -ENOMEM; in tilcdc_crtc_create()
1028 init_completion(&tilcdc_crtc->palette_loaded); in tilcdc_crtc_create()
1029 tilcdc_crtc->palette_base = dmam_alloc_coherent(dev->dev, in tilcdc_crtc_create()
1031 &tilcdc_crtc->palette_dma_handle, in tilcdc_crtc_create()
1033 if (!tilcdc_crtc->palette_base) in tilcdc_crtc_create()
1034 return -ENOMEM; in tilcdc_crtc_create()
1035 *tilcdc_crtc->palette_base = TILCDC_PALETTE_FIRST_ENTRY; in tilcdc_crtc_create()
1037 crtc = &tilcdc_crtc->base; in tilcdc_crtc_create()
1039 ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary); in tilcdc_crtc_create()
1043 mutex_init(&tilcdc_crtc->enable_lock); in tilcdc_crtc_create()
1045 init_waitqueue_head(&tilcdc_crtc->frame_done_wq); in tilcdc_crtc_create()
1047 spin_lock_init(&tilcdc_crtc->irq_lock); in tilcdc_crtc_create()
1048 INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work); in tilcdc_crtc_create()
1051 &tilcdc_crtc->primary, in tilcdc_crtc_create()
1060 if (priv->is_componentized) { in tilcdc_crtc_create()
1061 crtc->port = of_graph_get_port_by_id(dev->dev->of_node, 0); in tilcdc_crtc_create()
1062 if (!crtc->port) { /* This should never happen */ in tilcdc_crtc_create()
1063 dev_err(dev->dev, "Port node not found in %pOF\n", in tilcdc_crtc_create()
1064 dev->dev->of_node); in tilcdc_crtc_create()
1065 ret = -EINVAL; in tilcdc_crtc_create()
1070 priv->crtc = crtc; in tilcdc_crtc_create()