425 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val)  in dispc_vid_write()  argument
427 	void __iomem *base = dispc->base_vid[hw_plane];  in dispc_vid_write()
432 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg)  in dispc_vid_read()  argument
434 	void __iomem *base = dispc->base_vid[hw_plane];  in dispc_vid_read()
506 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx,  in VID_REG_GET()  argument
509 	return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end);  in VID_REG_GET()
512 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx,  in VID_REG_FLD_MOD()  argument
515 	dispc_vid_write(dispc, hw_plane, idx,  in VID_REG_FLD_MOD()
516 			FLD_MOD(dispc_vid_read(dispc, hw_plane, idx),  in VID_REG_FLD_MOD()
580 static dispc_irq_t dispc_vid_irq_from_raw(u32 stat, u32 hw_plane)  in dispc_vid_irq_from_raw()  argument
585 		vid_stat |= DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane);  in dispc_vid_irq_from_raw()
590 static u32 dispc_vid_irq_to_raw(dispc_irq_t vidstat, u32 hw_plane)  in dispc_vid_irq_to_raw()  argument
594 	if (vidstat & DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane))  in dispc_vid_irq_to_raw()
617 						u32 hw_plane)  in dispc_k2g_vid_read_irqstatus()  argument
619 	u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS);  in dispc_k2g_vid_read_irqstatus()
621 	return dispc_vid_irq_from_raw(stat, hw_plane);  in dispc_k2g_vid_read_irqstatus()
625 					  u32 hw_plane, dispc_irq_t vidstat)  in dispc_k2g_vid_write_irqstatus()  argument
627 	u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);  in dispc_k2g_vid_write_irqstatus()
629 	dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat);  in dispc_k2g_vid_write_irqstatus()
649 						u32 hw_plane)  in dispc_k2g_vid_read_irqenable()  argument
651 	u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE);  in dispc_k2g_vid_read_irqenable()
653 	return dispc_vid_irq_from_raw(stat, hw_plane);  in dispc_k2g_vid_read_irqenable()
657 					u32 hw_plane, dispc_irq_t vidstat)  in dispc_k2g_vid_set_irqenable()  argument
659 	u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);  in dispc_k2g_vid_set_irqenable()
661 	dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat);  in dispc_k2g_vid_set_irqenable()
732 					       u32 hw_plane)  in dispc_k3_vid_read_irqstatus()  argument
734 	u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane));  in dispc_k3_vid_read_irqstatus()
736 	return dispc_vid_irq_from_raw(stat, hw_plane);  in dispc_k3_vid_read_irqstatus()
740 					 u32 hw_plane, dispc_irq_t vidstat)  in dispc_k3_vid_write_irqstatus()  argument
742 	u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);  in dispc_k3_vid_write_irqstatus()
744 	dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat);  in dispc_k3_vid_write_irqstatus()
764 					       u32 hw_plane)  in dispc_k3_vid_read_irqenable()  argument
766 	u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane));  in dispc_k3_vid_read_irqenable()
768 	return dispc_vid_irq_from_raw(stat, hw_plane);  in dispc_k3_vid_read_irqenable()
772 				       u32 hw_plane, dispc_irq_t vidstat)  in dispc_k3_vid_set_irqenable()  argument
774 	u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);  in dispc_k3_vid_set_irqenable()
776 	dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat);  in dispc_k3_vid_set_irqenable()
1349 				    u32 hw_plane, u32 hw_videoport,  in dispc_k2g_ovr_set_plane()  argument
1353 	dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION,  in dispc_k2g_ovr_set_plane()
1358 				      u32 hw_plane, u32 hw_videoport,  in dispc_am65x_ovr_set_plane()  argument
1362 			hw_plane, 4, 1);  in dispc_am65x_ovr_set_plane()
1370 				      u32 hw_plane, u32 hw_videoport,  in dispc_j721e_ovr_set_plane()  argument
1374 			hw_plane, 4, 1);  in dispc_j721e_ovr_set_plane()
1381 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,  in dispc_ovr_set_plane()  argument
1386 		dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport,  in dispc_ovr_set_plane()
1392 		dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport,  in dispc_ovr_set_plane()
1396 		dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport,  in dispc_ovr_set_plane()
1494 static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,  in dispc_k2g_vid_write_csc()  argument
1513 		dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],  in dispc_k2g_vid_write_csc()
1517 static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,  in dispc_k3_vid_write_csc()  argument
1532 		dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],  in dispc_k3_vid_write_csc()
1614 static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane,  in dispc_vid_csc_setup()  argument
1627 		dispc_k2g_vid_write_csc(dispc, hw_plane, coef);  in dispc_vid_csc_setup()
1629 		dispc_k3_vid_write_csc(dispc, hw_plane, coef);  in dispc_vid_csc_setup()
1632 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane,  in dispc_vid_csc_enable()  argument
1635 	VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9);  in dispc_vid_csc_enable()
1653 				      u32 hw_plane,  in dispc_vid_write_fir_coefs()  argument
1684 		dispc_vid_write(dispc, hw_plane, reg, c0);  in dispc_vid_write_fir_coefs()
1696 		dispc_vid_write(dispc, hw_plane, reg, c12);  in dispc_vid_write_fir_coefs()
1886 				  u32 hw_plane,  in dispc_vid_set_scaling()  argument
1891 	VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,  in dispc_vid_set_scaling()
1895 	VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,  in dispc_vid_set_scaling()
1903 	VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,  in dispc_vid_set_scaling()
1908 			dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2,  in dispc_vid_set_scaling()
1910 			dispc_vid_write_fir_coefs(dispc, hw_plane,  in dispc_vid_set_scaling()
1915 			dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2,  in dispc_vid_set_scaling()
1917 			dispc_vid_write_fir_coefs(dispc, hw_plane,  in dispc_vid_set_scaling()
1924 		dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc);  in dispc_vid_set_scaling()
1925 		dispc_vid_write_fir_coefs(dispc, hw_plane,  in dispc_vid_set_scaling()
1931 		dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc);  in dispc_vid_set_scaling()
1932 		dispc_vid_write_fir_coefs(dispc, hw_plane,  in dispc_vid_set_scaling()
1986 					 u32 hw_plane, u32 fourcc)  in dispc_plane_set_pixel_format()  argument
1992 			VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,  in dispc_plane_set_pixel_format()
2024 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,  in dispc_plane_check()  argument
2028 	bool lite = dispc->feat->vid_lite[hw_plane];  in dispc_plane_check()
2041 				state->color_range, hw_plane);  in dispc_plane_check()
2050 				__func__, hw_plane,  in dispc_plane_check()
2095 void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,  in dispc_plane_setup()  argument
2099 	bool lite = dispc->feat->vid_lite[hw_plane];  in dispc_plane_setup()
2108 	dispc_plane_set_pixel_format(dispc, hw_plane, fourcc);  in dispc_plane_setup()
2110 	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff);  in dispc_plane_setup()
2111 	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32);  in dispc_plane_setup()
2112 	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff);  in dispc_plane_setup()
2113 	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32);  in dispc_plane_setup()
2115 	dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE,  in dispc_plane_setup()
2120 		dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,  in dispc_plane_setup()
2123 		dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,  in dispc_plane_setup()
2126 	dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC,  in dispc_plane_setup()
2136 		dispc_vid_write(dispc, hw_plane,  in dispc_plane_setup()
2138 		dispc_vid_write(dispc, hw_plane,  in dispc_plane_setup()
2140 		dispc_vid_write(dispc, hw_plane,  in dispc_plane_setup()
2142 		dispc_vid_write(dispc, hw_plane,  in dispc_plane_setup()
2145 		dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV,  in dispc_plane_setup()
2152 		dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE,  in dispc_plane_setup()
2156 		dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc);  in dispc_plane_setup()
2161 		dispc_vid_csc_setup(dispc, hw_plane, state);  in dispc_plane_setup()
2162 		dispc_vid_csc_enable(dispc, hw_plane, true);  in dispc_plane_setup()
2164 		dispc_vid_csc_enable(dispc, hw_plane, false);  in dispc_plane_setup()
2167 	dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA,  in dispc_plane_setup()
2171 		VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,  in dispc_plane_setup()
2174 		VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,  in dispc_plane_setup()
2178 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable)  in dispc_plane_enable()  argument
2180 	VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0);  in dispc_plane_enable()
2183 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane)  in dispc_vid_get_fifo_size()  argument
2185 	return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0);  in dispc_vid_get_fifo_size()
2189 					  u32 hw_plane, u32 low, u32 high)  in dispc_vid_set_mflag_threshold()  argument
2191 	dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD,  in dispc_vid_set_mflag_threshold()
2196 					u32 hw_plane, u32 low, u32 high)  in dispc_vid_set_buf_threshold()  argument
2198 	dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD,  in dispc_vid_set_buf_threshold()
2204 	unsigned int hw_plane;  in dispc_k2g_plane_init()  local
2213 	for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {  in dispc_k2g_plane_init()
2214 		u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);  in dispc_k2g_plane_init()
2229 			dispc->feat->vid_name[hw_plane],  in dispc_k2g_plane_init()
2235 		dispc_vid_set_buf_threshold(dispc, hw_plane,  in dispc_k2g_plane_init()
2237 		dispc_vid_set_mflag_threshold(dispc, hw_plane,  in dispc_k2g_plane_init()
2240 		dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);  in dispc_k2g_plane_init()
2247 		VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,  in dispc_k2g_plane_init()
2254 	unsigned int hw_plane;  in dispc_k3_plane_init()  local
2268 	for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {  in dispc_k3_plane_init()
2269 		u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);  in dispc_k3_plane_init()
2284 			dispc->feat->vid_name[hw_plane],  in dispc_k3_plane_init()
2290 		dispc_vid_set_buf_threshold(dispc, hw_plane,  in dispc_k3_plane_init()
2292 		dispc_vid_set_mflag_threshold(dispc, hw_plane,  in dispc_k3_plane_init()
2295 		dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);  in dispc_k3_plane_init()
2298 		VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,  in dispc_k3_plane_init()