Lines Matching refs:dispc
414 static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val) in dispc_write() argument
416 iowrite32(val, dispc->base_common + reg); in dispc_write()
419 static u32 dispc_read(struct dispc_device *dispc, u16 reg) in dispc_read() argument
421 return ioread32(dispc->base_common + reg); in dispc_read()
425 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) in dispc_vid_write() argument
427 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
432 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) in dispc_vid_read() argument
434 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
439 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport, in dispc_ovr_write() argument
442 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_write()
447 static u32 dispc_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) in dispc_ovr_read() argument
449 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_read()
454 static void dispc_vp_write(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_write() argument
457 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_write()
462 static u32 dispc_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) in dispc_vp_read() argument
464 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_read()
494 static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end) in REG_GET() argument
496 return FLD_GET(dispc_read(dispc, idx), start, end); in REG_GET()
499 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, in REG_FLD_MOD() argument
502 dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val, in REG_FLD_MOD()
506 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, in VID_REG_GET() argument
509 return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end); in VID_REG_GET()
512 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx, in VID_REG_FLD_MOD() argument
515 dispc_vid_write(dispc, hw_plane, idx, in VID_REG_FLD_MOD()
516 FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), in VID_REG_FLD_MOD()
520 static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, in VP_REG_GET() argument
523 return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end); in VP_REG_GET()
526 static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32 val, in VP_REG_FLD_MOD() argument
529 dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx), in VP_REG_FLD_MOD()
534 static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx, in OVR_REG_GET() argument
537 return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end); in OVR_REG_GET()
540 static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, in OVR_REG_FLD_MOD() argument
543 dispc_ovr_write(dispc, ovr, idx, in OVR_REG_FLD_MOD()
544 FLD_MOD(dispc_ovr_read(dispc, ovr, idx), in OVR_REG_FLD_MOD()
600 static dispc_irq_t dispc_k2g_vp_read_irqstatus(struct dispc_device *dispc, in dispc_k2g_vp_read_irqstatus() argument
603 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS); in dispc_k2g_vp_read_irqstatus()
608 static void dispc_k2g_vp_write_irqstatus(struct dispc_device *dispc, in dispc_k2g_vp_write_irqstatus() argument
613 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS, stat); in dispc_k2g_vp_write_irqstatus()
616 static dispc_irq_t dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc, in dispc_k2g_vid_read_irqstatus() argument
619 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS); in dispc_k2g_vid_read_irqstatus()
624 static void dispc_k2g_vid_write_irqstatus(struct dispc_device *dispc, in dispc_k2g_vid_write_irqstatus() argument
629 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat); in dispc_k2g_vid_write_irqstatus()
632 static dispc_irq_t dispc_k2g_vp_read_irqenable(struct dispc_device *dispc, in dispc_k2g_vp_read_irqenable() argument
635 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE); in dispc_k2g_vp_read_irqenable()
640 static void dispc_k2g_vp_set_irqenable(struct dispc_device *dispc, in dispc_k2g_vp_set_irqenable() argument
645 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE, stat); in dispc_k2g_vp_set_irqenable()
648 static dispc_irq_t dispc_k2g_vid_read_irqenable(struct dispc_device *dispc, in dispc_k2g_vid_read_irqenable() argument
651 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE); in dispc_k2g_vid_read_irqenable()
656 static void dispc_k2g_vid_set_irqenable(struct dispc_device *dispc, in dispc_k2g_vid_set_irqenable() argument
661 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat); in dispc_k2g_vid_set_irqenable()
664 static void dispc_k2g_clear_irqstatus(struct dispc_device *dispc, in dispc_k2g_clear_irqstatus() argument
667 dispc_k2g_vp_write_irqstatus(dispc, 0, mask); in dispc_k2g_clear_irqstatus()
668 dispc_k2g_vid_write_irqstatus(dispc, 0, mask); in dispc_k2g_clear_irqstatus()
672 dispc_irq_t dispc_k2g_read_and_clear_irqstatus(struct dispc_device *dispc) in dispc_k2g_read_and_clear_irqstatus() argument
677 dispc_write(dispc, DISPC_IRQSTATUS, in dispc_k2g_read_and_clear_irqstatus()
678 dispc_read(dispc, DISPC_IRQSTATUS)); in dispc_k2g_read_and_clear_irqstatus()
680 stat |= dispc_k2g_vp_read_irqstatus(dispc, 0); in dispc_k2g_read_and_clear_irqstatus()
681 stat |= dispc_k2g_vid_read_irqstatus(dispc, 0); in dispc_k2g_read_and_clear_irqstatus()
683 dispc_k2g_clear_irqstatus(dispc, stat); in dispc_k2g_read_and_clear_irqstatus()
688 static dispc_irq_t dispc_k2g_read_irqenable(struct dispc_device *dispc) in dispc_k2g_read_irqenable() argument
692 stat |= dispc_k2g_vp_read_irqenable(dispc, 0); in dispc_k2g_read_irqenable()
693 stat |= dispc_k2g_vid_read_irqenable(dispc, 0); in dispc_k2g_read_irqenable()
699 void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) in dispc_k2g_set_irqenable() argument
701 dispc_irq_t old_mask = dispc_k2g_read_irqenable(dispc); in dispc_k2g_set_irqenable()
704 dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & mask); in dispc_k2g_set_irqenable()
706 dispc_k2g_vp_set_irqenable(dispc, 0, mask); in dispc_k2g_set_irqenable()
707 dispc_k2g_vid_set_irqenable(dispc, 0, mask); in dispc_k2g_set_irqenable()
709 dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7)); in dispc_k2g_set_irqenable()
712 dispc_k2g_read_irqenable(dispc); in dispc_k2g_set_irqenable()
715 static dispc_irq_t dispc_k3_vp_read_irqstatus(struct dispc_device *dispc, in dispc_k3_vp_read_irqstatus() argument
718 u32 stat = dispc_read(dispc, DISPC_VP_IRQSTATUS(hw_videoport)); in dispc_k3_vp_read_irqstatus()
723 static void dispc_k3_vp_write_irqstatus(struct dispc_device *dispc, in dispc_k3_vp_write_irqstatus() argument
728 dispc_write(dispc, DISPC_VP_IRQSTATUS(hw_videoport), stat); in dispc_k3_vp_write_irqstatus()
731 static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc, in dispc_k3_vid_read_irqstatus() argument
734 u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane)); in dispc_k3_vid_read_irqstatus()
739 static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc, in dispc_k3_vid_write_irqstatus() argument
744 dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat); in dispc_k3_vid_write_irqstatus()
747 static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc, in dispc_k3_vp_read_irqenable() argument
750 u32 stat = dispc_read(dispc, DISPC_VP_IRQENABLE(hw_videoport)); in dispc_k3_vp_read_irqenable()
755 static void dispc_k3_vp_set_irqenable(struct dispc_device *dispc, in dispc_k3_vp_set_irqenable() argument
760 dispc_write(dispc, DISPC_VP_IRQENABLE(hw_videoport), stat); in dispc_k3_vp_set_irqenable()
763 static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc, in dispc_k3_vid_read_irqenable() argument
766 u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane)); in dispc_k3_vid_read_irqenable()
771 static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc, in dispc_k3_vid_set_irqenable() argument
776 dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat); in dispc_k3_vid_set_irqenable()
780 void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask) in dispc_k3_clear_irqstatus() argument
785 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_clear_irqstatus()
787 dispc_k3_vp_write_irqstatus(dispc, i, clearmask); in dispc_k3_clear_irqstatus()
791 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_clear_irqstatus()
793 dispc_k3_vid_write_irqstatus(dispc, i, clearmask); in dispc_k3_clear_irqstatus()
797 if (dispc->feat->subrev == DISPC_K2G) in dispc_k3_clear_irqstatus()
800 dispc_write(dispc, DISPC_IRQSTATUS, top_clear); in dispc_k3_clear_irqstatus()
803 dispc_read(dispc, DISPC_IRQSTATUS); in dispc_k3_clear_irqstatus()
807 dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc) in dispc_k3_read_and_clear_irqstatus() argument
812 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_and_clear_irqstatus()
813 status |= dispc_k3_vp_read_irqstatus(dispc, i); in dispc_k3_read_and_clear_irqstatus()
815 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_and_clear_irqstatus()
816 status |= dispc_k3_vid_read_irqstatus(dispc, i); in dispc_k3_read_and_clear_irqstatus()
818 dispc_k3_clear_irqstatus(dispc, status); in dispc_k3_read_and_clear_irqstatus()
823 static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc) in dispc_k3_read_irqenable() argument
828 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_irqenable()
829 enable |= dispc_k3_vp_read_irqenable(dispc, i); in dispc_k3_read_irqenable()
831 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_irqenable()
832 enable |= dispc_k3_vid_read_irqenable(dispc, i); in dispc_k3_read_irqenable()
837 static void dispc_k3_set_irqenable(struct dispc_device *dispc, in dispc_k3_set_irqenable() argument
844 old_mask = dispc_k3_read_irqenable(dispc); in dispc_k3_set_irqenable()
847 dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & mask); in dispc_k3_set_irqenable()
849 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_set_irqenable()
850 dispc_k3_vp_set_irqenable(dispc, i, mask); in dispc_k3_set_irqenable()
857 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_set_irqenable()
858 dispc_k3_vid_set_irqenable(dispc, i, mask); in dispc_k3_set_irqenable()
866 dispc_write(dispc, DISPC_IRQENABLE_SET, main_enable); in dispc_k3_set_irqenable()
869 dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable); in dispc_k3_set_irqenable()
872 dispc_read(dispc, DISPC_IRQENABLE_SET); in dispc_k3_set_irqenable()
875 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc) in dispc_read_and_clear_irqstatus() argument
877 switch (dispc->feat->subrev) { in dispc_read_and_clear_irqstatus()
879 return dispc_k2g_read_and_clear_irqstatus(dispc); in dispc_read_and_clear_irqstatus()
884 return dispc_k3_read_and_clear_irqstatus(dispc); in dispc_read_and_clear_irqstatus()
891 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) in dispc_set_irqenable() argument
893 switch (dispc->feat->subrev) { in dispc_set_irqenable()
895 dispc_k2g_set_irqenable(dispc, mask); in dispc_set_irqenable()
901 dispc_k3_set_irqenable(dispc, mask); in dispc_set_irqenable()
931 struct dispc_bus_format *dispc_vp_find_bus_fmt(struct dispc_device *dispc, in dispc_vp_find_bus_fmt() argument
945 int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_bus_check() argument
951 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_bus_check()
954 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n", in dispc_vp_bus_check()
959 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI && in dispc_vp_bus_check()
961 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n", in dispc_vp_bus_check()
962 __func__, dispc->feat->vp_name[hw_videoport]); in dispc_vp_bus_check()
969 static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power) in dispc_oldi_tx_power() argument
973 if (WARN_ON(!dispc->oldi_io_ctrl)) in dispc_oldi_tx_power()
976 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, in dispc_oldi_tx_power()
978 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, in dispc_oldi_tx_power()
980 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, in dispc_oldi_tx_power()
982 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, in dispc_oldi_tx_power()
984 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, in dispc_oldi_tx_power()
988 static void dispc_set_num_datalines(struct dispc_device *dispc, in dispc_set_num_datalines() argument
1011 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8); in dispc_set_num_datalines()
1014 static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, in dispc_enable_oldi() argument
1029 dev_warn(dispc->dev, "%s: %d port width not supported\n", in dispc_enable_oldi()
1040 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); in dispc_enable_oldi()
1042 while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) && in dispc_enable_oldi()
1046 if (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS))) in dispc_enable_oldi()
1047 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n", in dispc_enable_oldi()
1051 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_prepare() argument
1057 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_prepare()
1063 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_prepare()
1064 dispc_oldi_tx_power(dispc, true); in dispc_vp_prepare()
1066 dispc_enable_oldi(dispc, hw_videoport, fmt); in dispc_vp_prepare()
1070 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_enable() argument
1079 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_enable()
1085 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width); in dispc_vp_enable()
1095 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H, in dispc_vp_enable()
1100 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V, in dispc_vp_enable()
1122 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) in dispc_vp_enable()
1125 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, in dispc_vp_enable()
1134 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, in dispc_vp_enable()
1138 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); in dispc_vp_enable()
1141 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_disable() argument
1143 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0); in dispc_vp_disable()
1146 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_unprepare() argument
1148 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_unprepare()
1149 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0); in dispc_vp_unprepare()
1151 dispc_oldi_tx_power(dispc, false); in dispc_vp_unprepare()
1155 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_go_busy() argument
1157 return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5); in dispc_vp_go_busy()
1160 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_go() argument
1162 WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5)); in dispc_vp_go()
1163 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5); in dispc_vp_go()
1206 static void dispc_vp_set_default_color(struct dispc_device *dispc, in dispc_vp_set_default_color() argument
1213 dispc_ovr_write(dispc, hw_videoport, in dispc_vp_set_default_color()
1215 dispc_ovr_write(dispc, hw_videoport, in dispc_vp_set_default_color()
1219 enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, in dispc_vp_mode_valid() argument
1227 bus_type = dispc->feat->vp_bus_type[hw_videoport]; in dispc_vp_mode_valid()
1229 max_pclk = dispc->feat->max_pclk_khz[bus_type]; in dispc_vp_mode_valid()
1234 if (mode->clock < dispc->feat->min_pclk_khz) in dispc_vp_mode_valid()
1278 if (dispc->memory_bandwidth_limit) { in dispc_vp_mode_valid()
1286 if (dispc->memory_bandwidth_limit < bandwidth) in dispc_vp_mode_valid()
1293 int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_enable_clk() argument
1295 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]); in dispc_vp_enable_clk()
1298 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__, in dispc_vp_enable_clk()
1304 void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_disable_clk() argument
1306 clk_disable_unprepare(dispc->vp_clk[hw_videoport]); in dispc_vp_disable_clk()
1321 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_set_clk_rate() argument
1327 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); in dispc_vp_set_clk_rate()
1329 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n", in dispc_vp_set_clk_rate()
1334 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]); in dispc_vp_set_clk_rate()
1337 dev_warn(dispc->dev, in dispc_vp_set_clk_rate()
1341 dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n", in dispc_vp_set_clk_rate()
1342 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate); in dispc_vp_set_clk_rate()
1348 static void dispc_k2g_ovr_set_plane(struct dispc_device *dispc, in dispc_k2g_ovr_set_plane() argument
1353 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION, in dispc_k2g_ovr_set_plane()
1357 static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc, in dispc_am65x_ovr_set_plane() argument
1361 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_am65x_ovr_set_plane()
1363 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_am65x_ovr_set_plane()
1365 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_am65x_ovr_set_plane()
1369 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc, in dispc_j721e_ovr_set_plane() argument
1373 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_j721e_ovr_set_plane()
1375 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), in dispc_j721e_ovr_set_plane()
1377 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), in dispc_j721e_ovr_set_plane()
1381 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, in dispc_ovr_set_plane() argument
1384 switch (dispc->feat->subrev) { in dispc_ovr_set_plane()
1386 dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport, in dispc_ovr_set_plane()
1392 dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, in dispc_ovr_set_plane()
1396 dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport, in dispc_ovr_set_plane()
1405 void dispc_ovr_enable_layer(struct dispc_device *dispc, in dispc_ovr_enable_layer() argument
1408 if (dispc->feat->subrev == DISPC_K2G) in dispc_ovr_enable_layer()
1411 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_ovr_enable_layer()
1494 static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, in dispc_k2g_vid_write_csc() argument
1509 dev_warn(dispc->dev, "%s: No post offset support for %s\n", in dispc_k2g_vid_write_csc()
1513 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i], in dispc_k2g_vid_write_csc()
1517 static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, in dispc_k3_vid_write_csc() argument
1532 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i], in dispc_k3_vid_write_csc()
1614 static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane, in dispc_vid_csc_setup() argument
1621 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n", in dispc_vid_csc_setup()
1626 if (dispc->feat->subrev == DISPC_K2G) in dispc_vid_csc_setup()
1627 dispc_k2g_vid_write_csc(dispc, hw_plane, coef); in dispc_vid_csc_setup()
1629 dispc_k3_vid_write_csc(dispc, hw_plane, coef); in dispc_vid_csc_setup()
1632 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, in dispc_vid_csc_enable() argument
1635 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9); in dispc_vid_csc_enable()
1652 static void dispc_vid_write_fir_coefs(struct dispc_device *dispc, in dispc_vid_write_fir_coefs() argument
1676 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__); in dispc_vid_write_fir_coefs()
1684 dispc_vid_write(dispc, hw_plane, reg, c0); in dispc_vid_write_fir_coefs()
1696 dispc_vid_write(dispc, hw_plane, reg, c12); in dispc_vid_write_fir_coefs()
1721 static int dispc_vid_calc_scaling(struct dispc_device *dispc, in dispc_vid_calc_scaling() argument
1726 const struct dispc_features_scaling *f = &dispc->feat->scaling; in dispc_vid_calc_scaling()
1775 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1788 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1805 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1826 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1844 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1860 sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1868 sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1875 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc, in dispc_vid_calc_scaling()
1879 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc, in dispc_vid_calc_scaling()
1885 static void dispc_vid_set_scaling(struct dispc_device *dispc, in dispc_vid_set_scaling() argument
1891 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_vid_set_scaling()
1895 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_vid_set_scaling()
1903 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_vid_set_scaling()
1908 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, in dispc_vid_set_scaling()
1910 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1915 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2, in dispc_vid_set_scaling()
1917 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1924 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc); in dispc_vid_set_scaling()
1925 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1931 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc); in dispc_vid_set_scaling()
1932 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1985 static void dispc_plane_set_pixel_format(struct dispc_device *dispc, in dispc_plane_set_pixel_format() argument
1992 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_plane_set_pixel_format()
2002 const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len) in dispc_plane_formats() argument
2004 WARN_ON(!dispc->fourccs); in dispc_plane_formats()
2006 *len = dispc->num_fourccs; in dispc_plane_formats()
2008 return dispc->fourccs; in dispc_plane_formats()
2024 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, in dispc_plane_check() argument
2028 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_check()
2038 dev_dbg(dispc->dev, in dispc_plane_check()
2048 dev_dbg(dispc->dev, in dispc_plane_check()
2055 ret = dispc_vid_calc_scaling(dispc, state, &scaling, false); in dispc_plane_check()
2095 void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, in dispc_plane_setup() argument
2099 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_setup()
2106 dispc_vid_calc_scaling(dispc, state, &scale, lite); in dispc_plane_setup()
2108 dispc_plane_set_pixel_format(dispc, hw_plane, fourcc); in dispc_plane_setup()
2110 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff); in dispc_plane_setup()
2111 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32); in dispc_plane_setup()
2112 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff); in dispc_plane_setup()
2113 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32); in dispc_plane_setup()
2115 dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE, in dispc_plane_setup()
2120 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, in dispc_plane_setup()
2123 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, in dispc_plane_setup()
2126 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC, in dispc_plane_setup()
2136 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2138 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2140 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2142 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2145 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV, in dispc_plane_setup()
2152 dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE, in dispc_plane_setup()
2156 dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc); in dispc_plane_setup()
2161 dispc_vid_csc_setup(dispc, hw_plane, state); in dispc_plane_setup()
2162 dispc_vid_csc_enable(dispc, hw_plane, true); in dispc_plane_setup()
2164 dispc_vid_csc_enable(dispc, hw_plane, false); in dispc_plane_setup()
2167 dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, in dispc_plane_setup()
2171 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, in dispc_plane_setup()
2174 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, in dispc_plane_setup()
2178 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) in dispc_plane_enable() argument
2180 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); in dispc_plane_enable()
2183 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane) in dispc_vid_get_fifo_size() argument
2185 return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0); in dispc_vid_get_fifo_size()
2188 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, in dispc_vid_set_mflag_threshold() argument
2191 dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, in dispc_vid_set_mflag_threshold()
2195 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc, in dispc_vid_set_buf_threshold() argument
2198 dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD, in dispc_vid_set_buf_threshold()
2202 static void dispc_k2g_plane_init(struct dispc_device *dispc) in dispc_k2g_plane_init() argument
2206 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k2g_plane_init()
2209 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); in dispc_k2g_plane_init()
2211 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); in dispc_k2g_plane_init()
2213 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k2g_plane_init()
2214 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); in dispc_k2g_plane_init()
2227 dev_dbg(dispc->dev, in dispc_k2g_plane_init()
2229 dispc->feat->vid_name[hw_plane], in dispc_k2g_plane_init()
2235 dispc_vid_set_buf_threshold(dispc, hw_plane, in dispc_k2g_plane_init()
2237 dispc_vid_set_mflag_threshold(dispc, hw_plane, in dispc_k2g_plane_init()
2240 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); in dispc_k2g_plane_init()
2247 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, in dispc_k2g_plane_init()
2252 static void dispc_k3_plane_init(struct dispc_device *dispc) in dispc_k3_plane_init() argument
2258 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k3_plane_init()
2260 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0); in dispc_k3_plane_init()
2261 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3); in dispc_k3_plane_init()
2264 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); in dispc_k3_plane_init()
2266 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); in dispc_k3_plane_init()
2268 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k3_plane_init()
2269 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); in dispc_k3_plane_init()
2282 dev_dbg(dispc->dev, in dispc_k3_plane_init()
2284 dispc->feat->vid_name[hw_plane], in dispc_k3_plane_init()
2290 dispc_vid_set_buf_threshold(dispc, hw_plane, in dispc_k3_plane_init()
2292 dispc_vid_set_mflag_threshold(dispc, hw_plane, in dispc_k3_plane_init()
2295 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); in dispc_k3_plane_init()
2298 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, in dispc_k3_plane_init()
2303 static void dispc_plane_init(struct dispc_device *dispc) in dispc_plane_init() argument
2305 switch (dispc->feat->subrev) { in dispc_plane_init()
2307 dispc_k2g_plane_init(dispc); in dispc_plane_init()
2313 dispc_k3_plane_init(dispc); in dispc_plane_init()
2320 static void dispc_vp_init(struct dispc_device *dispc) in dispc_vp_init() argument
2324 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_vp_init()
2327 for (i = 0; i < dispc->feat->num_vps; i++) in dispc_vp_init()
2328 VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2); in dispc_vp_init()
2331 static void dispc_initial_config(struct dispc_device *dispc) in dispc_initial_config() argument
2333 dispc_plane_init(dispc); in dispc_initial_config()
2334 dispc_vp_init(dispc); in dispc_initial_config()
2337 if (dispc->feat->subrev == DISPC_J721E) { in dispc_initial_config()
2338 dispc_write(dispc, DISPC_CONNECTIONS, in dispc_initial_config()
2345 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc, in dispc_k2g_vp_write_gamma_table() argument
2348 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_k2g_vp_write_gamma_table()
2349 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_k2g_vp_write_gamma_table()
2352 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_k2g_vp_write_gamma_table()
2354 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_k2g_vp_write_gamma_table()
2362 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_GAMMA_TABLE, in dispc_k2g_vp_write_gamma_table()
2367 static void dispc_am65x_vp_write_gamma_table(struct dispc_device *dispc, in dispc_am65x_vp_write_gamma_table() argument
2370 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_am65x_vp_write_gamma_table()
2371 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_am65x_vp_write_gamma_table()
2374 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_am65x_vp_write_gamma_table()
2376 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_am65x_vp_write_gamma_table()
2384 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v); in dispc_am65x_vp_write_gamma_table()
2388 static void dispc_j721e_vp_write_gamma_table(struct dispc_device *dispc, in dispc_j721e_vp_write_gamma_table() argument
2391 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_j721e_vp_write_gamma_table()
2392 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_j721e_vp_write_gamma_table()
2395 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_j721e_vp_write_gamma_table()
2397 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT)) in dispc_j721e_vp_write_gamma_table()
2406 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v); in dispc_j721e_vp_write_gamma_table()
2410 static void dispc_vp_write_gamma_table(struct dispc_device *dispc, in dispc_vp_write_gamma_table() argument
2413 switch (dispc->feat->subrev) { in dispc_vp_write_gamma_table()
2415 dispc_k2g_vp_write_gamma_table(dispc, hw_videoport); in dispc_vp_write_gamma_table()
2420 dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); in dispc_vp_write_gamma_table()
2423 dispc_j721e_vp_write_gamma_table(dispc, hw_videoport); in dispc_vp_write_gamma_table()
2436 static void dispc_vp_set_gamma(struct dispc_device *dispc, in dispc_vp_set_gamma() argument
2441 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_vp_set_gamma()
2442 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_vp_set_gamma()
2446 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n", in dispc_vp_set_gamma()
2449 if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT) in dispc_vp_set_gamma()
2483 dispc_vp_write_gamma_table(dispc, hw_videoport); in dispc_vp_set_gamma()
2530 static void dispc_k2g_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport, in dispc_k2g_vp_write_csc() argument
2543 dispc_vp_write(dispc, hw_videoport, dispc_vp_cpr_coef_reg[i], in dispc_k2g_vp_write_csc()
2547 static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, in dispc_k2g_vp_set_ctm() argument
2556 dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr); in dispc_k2g_vp_set_ctm()
2560 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, in dispc_k2g_vp_set_ctm()
2595 static void dispc_k3_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport, in dispc_k3_vp_write_csc() argument
2609 dispc_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i], in dispc_k3_vp_write_csc()
2613 static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, in dispc_k3_vp_set_ctm() argument
2622 dispc_k3_vp_write_csc(dispc, hw_videoport, &csc); in dispc_k3_vp_set_ctm()
2626 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, in dispc_k3_vp_set_ctm()
2630 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc, in dispc_vp_set_color_mgmt() argument
2647 dispc_vp_set_gamma(dispc, hw_videoport, lut, length); in dispc_vp_set_color_mgmt()
2652 if (dispc->feat->subrev == DISPC_K2G) in dispc_vp_set_color_mgmt()
2653 dispc_k2g_vp_set_ctm(dispc, hw_videoport, ctm); in dispc_vp_set_color_mgmt()
2655 dispc_k3_vp_set_ctm(dispc, hw_videoport, ctm); in dispc_vp_set_color_mgmt()
2658 void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_setup() argument
2661 dispc_vp_set_default_color(dispc, hw_videoport, 0); in dispc_vp_setup()
2662 dispc_vp_set_color_mgmt(dispc, hw_videoport, state, newmodeset); in dispc_vp_setup()
2665 int dispc_runtime_suspend(struct dispc_device *dispc) in dispc_runtime_suspend() argument
2667 dev_dbg(dispc->dev, "suspend\n"); in dispc_runtime_suspend()
2669 dispc->is_enabled = false; in dispc_runtime_suspend()
2671 clk_disable_unprepare(dispc->fclk); in dispc_runtime_suspend()
2676 int dispc_runtime_resume(struct dispc_device *dispc) in dispc_runtime_resume() argument
2678 dev_dbg(dispc->dev, "resume\n"); in dispc_runtime_resume()
2680 clk_prepare_enable(dispc->fclk); in dispc_runtime_resume()
2682 if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) == 0) in dispc_runtime_resume()
2683 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); in dispc_runtime_resume()
2685 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", in dispc_runtime_resume()
2686 dispc_read(dispc, DSS_REVISION)); in dispc_runtime_resume()
2688 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2689 REG_GET(dispc, DSS_SYSSTATUS, 1, 1), in dispc_runtime_resume()
2690 REG_GET(dispc, DSS_SYSSTATUS, 2, 2), in dispc_runtime_resume()
2691 REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); in dispc_runtime_resume()
2693 if (dispc->feat->subrev == DISPC_AM625 || in dispc_runtime_resume()
2694 dispc->feat->subrev == DISPC_AM65X) in dispc_runtime_resume()
2695 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2696 REG_GET(dispc, DSS_SYSSTATUS, 5, 5), in dispc_runtime_resume()
2697 REG_GET(dispc, DSS_SYSSTATUS, 6, 6), in dispc_runtime_resume()
2698 REG_GET(dispc, DSS_SYSSTATUS, 7, 7)); in dispc_runtime_resume()
2700 dev_dbg(dispc->dev, "DISPC IDLE %d\n", in dispc_runtime_resume()
2701 REG_GET(dispc, DSS_SYSSTATUS, 9, 9)); in dispc_runtime_resume()
2703 dispc_initial_config(dispc); in dispc_runtime_resume()
2705 dispc->is_enabled = true; in dispc_runtime_resume()
2707 tidss_irq_resume(dispc->tidss); in dispc_runtime_resume()
2716 tidss->dispc = NULL; in dispc_remove()
2736 struct dispc_device *dispc) in dispc_init_am65x_oldi_io_ctrl() argument
2738 dispc->oldi_io_ctrl = in dispc_init_am65x_oldi_io_ctrl()
2741 if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) { in dispc_init_am65x_oldi_io_ctrl()
2742 dispc->oldi_io_ctrl = NULL; in dispc_init_am65x_oldi_io_ctrl()
2743 } else if (IS_ERR(dispc->oldi_io_ctrl)) { in dispc_init_am65x_oldi_io_ctrl()
2745 __func__, PTR_ERR(dispc->oldi_io_ctrl)); in dispc_init_am65x_oldi_io_ctrl()
2746 return PTR_ERR(dispc->oldi_io_ctrl); in dispc_init_am65x_oldi_io_ctrl()
2751 static void dispc_init_errata(struct dispc_device *dispc) in dispc_init_errata() argument
2759 dispc->errata.i2000 = true; in dispc_init_errata()
2760 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n"); in dispc_init_errata()
2768 static void dispc_softreset_k2g(struct dispc_device *dispc) in dispc_softreset_k2g() argument
2770 dispc_set_irqenable(dispc, 0); in dispc_softreset_k2g()
2771 dispc_read_and_clear_irqstatus(dispc); in dispc_softreset_k2g()
2773 for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx) in dispc_softreset_k2g()
2774 VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0); in dispc_softreset_k2g()
2777 static int dispc_softreset(struct dispc_device *dispc) in dispc_softreset() argument
2782 if (dispc->feat->subrev == DISPC_K2G) { in dispc_softreset()
2783 dispc_softreset_k2g(dispc); in dispc_softreset()
2788 REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1); in dispc_softreset()
2790 ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, in dispc_softreset()
2793 dev_err(dispc->dev, "failed to reset dispc\n"); in dispc_softreset()
2800 static int dispc_init_hw(struct dispc_device *dispc) in dispc_init_hw() argument
2802 struct device *dev = dispc->dev; in dispc_init_hw()
2811 ret = clk_prepare_enable(dispc->fclk); in dispc_init_hw()
2817 ret = dispc_softreset(dispc); in dispc_init_hw()
2821 clk_disable_unprepare(dispc->fclk); in dispc_init_hw()
2831 clk_disable_unprepare(dispc->fclk); in dispc_init_hw()
2847 struct dispc_device *dispc; in dispc_init() local
2864 dispc = devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL); in dispc_init()
2865 if (!dispc) in dispc_init()
2868 dispc->tidss = tidss; in dispc_init()
2869 dispc->dev = dev; in dispc_init()
2870 dispc->feat = feat; in dispc_init()
2872 dispc_init_errata(dispc); in dispc_init()
2874 dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats), in dispc_init()
2875 sizeof(*dispc->fourccs), GFP_KERNEL); in dispc_init()
2876 if (!dispc->fourccs) in dispc_init()
2881 if (dispc->errata.i2000 && in dispc_init()
2885 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc; in dispc_init()
2888 dispc->num_fourccs = num_fourccs; in dispc_init()
2890 dispc_common_regmap = dispc->feat->common_regs; in dispc_init()
2892 r = dispc_iomap_resource(pdev, dispc->feat->common, in dispc_init()
2893 &dispc->base_common); in dispc_init()
2897 for (i = 0; i < dispc->feat->num_planes; i++) { in dispc_init()
2898 r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i], in dispc_init()
2899 &dispc->base_vid[i]); in dispc_init()
2904 for (i = 0; i < dispc->feat->num_vps; i++) { in dispc_init()
2905 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; in dispc_init()
2909 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i], in dispc_init()
2910 &dispc->base_ovr[i]); in dispc_init()
2914 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i], in dispc_init()
2915 &dispc->base_vp[i]); in dispc_init()
2919 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]); in dispc_init()
2922 dispc->feat->vpclk_name[i], PTR_ERR(clk)); in dispc_init()
2925 dispc->vp_clk[i] = clk; in dispc_init()
2932 dispc->vp_data[i].gamma_table = gamma_table; in dispc_init()
2936 r = dispc_init_am65x_oldi_io_ctrl(dev, dispc); in dispc_init()
2941 dispc->fclk = devm_clk_get(dev, "fck"); in dispc_init()
2942 if (IS_ERR(dispc->fclk)) { in dispc_init()
2944 __func__, PTR_ERR(dispc->fclk)); in dispc_init()
2945 return PTR_ERR(dispc->fclk); in dispc_init()
2947 dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk)); in dispc_init()
2949 of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", in dispc_init()
2950 &dispc->memory_bandwidth_limit); in dispc_init()
2952 r = dispc_init_hw(dispc); in dispc_init()
2956 tidss->dispc = dispc; in dispc_init()