Lines Matching +full:src +full:- +full:coef
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
9 #include <linux/dma-mapping.h>
14 #include <linux/media-bus-format.h>
79 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
82 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
155 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
158 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
244 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
247 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
292 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
295 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
345 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
348 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
416 iowrite32(val, dispc->base_common + reg); in dispc_write()
421 return ioread32(dispc->base_common + reg); in dispc_read()
427 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
434 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
442 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_write()
449 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_read()
457 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_write()
464 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_read()
476 return ((1 << (start - end + 1)) - 1) << end; in FLD_MASK()
785 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_clear_irqstatus()
791 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_clear_irqstatus()
797 if (dispc->feat->subrev == DISPC_K2G) in dispc_k3_clear_irqstatus()
812 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_and_clear_irqstatus()
815 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_and_clear_irqstatus()
828 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_irqenable()
831 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_irqenable()
849 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_set_irqenable()
857 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_set_irqenable()
877 switch (dispc->feat->subrev) { in dispc_read_and_clear_irqstatus()
893 switch (dispc->feat->subrev) { in dispc_set_irqenable()
951 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_bus_check()
952 tstate->bus_flags); in dispc_vp_bus_check()
954 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n", in dispc_vp_bus_check()
955 __func__, tstate->bus_format); in dispc_vp_bus_check()
956 return -EINVAL; in dispc_vp_bus_check()
959 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI && in dispc_vp_bus_check()
960 fmt->is_oldi_fmt) { in dispc_vp_bus_check()
961 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n", in dispc_vp_bus_check()
962 __func__, dispc->feat->vp_name[hw_videoport]); in dispc_vp_bus_check()
963 return -EINVAL; in dispc_vp_bus_check()
973 if (WARN_ON(!dispc->oldi_io_ctrl)) in dispc_oldi_tx_power()
976 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, in dispc_oldi_tx_power()
978 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, in dispc_oldi_tx_power()
980 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, in dispc_oldi_tx_power()
982 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, in dispc_oldi_tx_power()
984 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, in dispc_oldi_tx_power()
1022 * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC in dispc_enable_oldi()
1026 if (fmt->data_width == 24) in dispc_enable_oldi()
1028 else if (fmt->data_width != 18) in dispc_enable_oldi()
1029 dev_warn(dispc->dev, "%s: %d port width not supported\n", in dispc_enable_oldi()
1030 __func__, fmt->data_width); in dispc_enable_oldi()
1034 oldi_cfg = FLD_MOD(oldi_cfg, fmt->oldi_mode_reg_val, 3, 1); in dispc_enable_oldi()
1047 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n", in dispc_enable_oldi()
1057 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_prepare()
1058 tstate->bus_flags); in dispc_vp_prepare()
1063 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_prepare()
1073 const struct drm_display_mode *mode = &state->adjusted_mode; in dispc_vp_enable()
1079 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_enable()
1080 tstate->bus_flags); in dispc_vp_enable()
1085 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width); in dispc_vp_enable()
1087 hfp = mode->hsync_start - mode->hdisplay; in dispc_vp_enable()
1088 hsw = mode->hsync_end - mode->hsync_start; in dispc_vp_enable()
1089 hbp = mode->htotal - mode->hsync_end; in dispc_vp_enable()
1091 vfp = mode->vsync_start - mode->vdisplay; in dispc_vp_enable()
1092 vsw = mode->vsync_end - mode->vsync_start; in dispc_vp_enable()
1093 vbp = mode->vtotal - mode->vsync_end; in dispc_vp_enable()
1096 FLD_VAL(hsw - 1, 7, 0) | in dispc_vp_enable()
1097 FLD_VAL(hfp - 1, 19, 8) | in dispc_vp_enable()
1098 FLD_VAL(hbp - 1, 31, 20)); in dispc_vp_enable()
1101 FLD_VAL(vsw - 1, 7, 0) | in dispc_vp_enable()
1105 ivs = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); in dispc_vp_enable()
1107 ihs = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); in dispc_vp_enable()
1109 ieo = !!(tstate->bus_flags & DRM_BUS_FLAG_DE_LOW); in dispc_vp_enable()
1111 ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); in dispc_vp_enable()
1116 rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE); in dispc_vp_enable()
1122 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) in dispc_vp_enable()
1135 FLD_VAL(mode->hdisplay - 1, 11, 0) | in dispc_vp_enable()
1136 FLD_VAL(mode->vdisplay - 1, 27, 16)); in dispc_vp_enable()
1148 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_unprepare()
1227 bus_type = dispc->feat->vp_bus_type[hw_videoport]; in dispc_vp_mode_valid()
1229 max_pclk = dispc->feat->max_pclk_khz[bus_type]; in dispc_vp_mode_valid()
1234 if (mode->clock < dispc->feat->min_pclk_khz) in dispc_vp_mode_valid()
1237 if (mode->clock > max_pclk) in dispc_vp_mode_valid()
1240 if (mode->hdisplay > 4096) in dispc_vp_mode_valid()
1243 if (mode->vdisplay > 4096) in dispc_vp_mode_valid()
1247 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dispc_vp_mode_valid()
1253 * - YUV output selected (BT656, BT1120) in dispc_vp_mode_valid()
1254 * - Dithering enabled in dispc_vp_mode_valid()
1255 * - TDM with TDMCycleFormat == 3 in dispc_vp_mode_valid()
1258 if ((mode->hdisplay % 2) != 0) in dispc_vp_mode_valid()
1261 hfp = mode->hsync_start - mode->hdisplay; in dispc_vp_mode_valid()
1262 hsw = mode->hsync_end - mode->hsync_start; in dispc_vp_mode_valid()
1263 hbp = mode->htotal - mode->hsync_end; in dispc_vp_mode_valid()
1265 vfp = mode->vsync_start - mode->vdisplay; in dispc_vp_mode_valid()
1266 vsw = mode->vsync_end - mode->vsync_start; in dispc_vp_mode_valid()
1267 vbp = mode->vtotal - mode->vsync_end; in dispc_vp_mode_valid()
1278 if (dispc->memory_bandwidth_limit) { in dispc_vp_mode_valid()
1282 bandwidth = 1000 * mode->clock; in dispc_vp_mode_valid()
1283 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; in dispc_vp_mode_valid()
1284 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); in dispc_vp_mode_valid()
1286 if (dispc->memory_bandwidth_limit < bandwidth) in dispc_vp_mode_valid()
1295 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]); in dispc_vp_enable_clk()
1298 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__, in dispc_vp_enable_clk()
1306 clk_disable_unprepare(dispc->vp_clk[hw_videoport]); in dispc_vp_disable_clk()
1318 return (unsigned int)(abs(((rr - r) * 100) / r)); in dispc_pclk_diff()
1327 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); in dispc_vp_set_clk_rate()
1329 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n", in dispc_vp_set_clk_rate()
1334 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]); in dispc_vp_set_clk_rate()
1337 dev_warn(dispc->dev, in dispc_vp_set_clk_rate()
1341 dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n", in dispc_vp_set_clk_rate()
1342 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate); in dispc_vp_set_clk_rate()
1384 switch (dispc->feat->subrev) { in dispc_ovr_set_plane()
1408 if (dispc->feat->subrev == DISPC_K2G) in dispc_ovr_enable_layer()
1449 regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]); in dispc_csc_offset_regval()
1450 regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]); in dispc_csc_offset_regval()
1451 regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]); in dispc_csc_offset_regval()
1459 regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); in dispc_csc_yuv2rgb_regval()
1460 regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); in dispc_csc_yuv2rgb_regval()
1461 regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]); in dispc_csc_yuv2rgb_regval()
1462 regval[3] = CVAL(csc->m[CSC_BY], csc->m[CSC_BCR]); in dispc_csc_yuv2rgb_regval()
1463 regval[4] = CVAL(csc->m[CSC_BCB], 0); in dispc_csc_yuv2rgb_regval()
1471 regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]); in dispc_csc_rgb2yuv_regval()
1472 regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CRR]); in dispc_csc_rgb2yuv_regval()
1473 regval[2] = CVAL(csc->m[CSC_CRG], csc->m[CSC_CRB]); in dispc_csc_rgb2yuv_regval()
1474 regval[3] = CVAL(csc->m[CSC_CBR], csc->m[CSC_CBG]); in dispc_csc_rgb2yuv_regval()
1475 regval[4] = CVAL(csc->m[CSC_CBB], 0); in dispc_csc_rgb2yuv_regval()
1483 regval[0] = CVAL(csc->m[CSC_RR], csc->m[CSC_RG]); in dispc_csc_cpr_regval()
1484 regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]); in dispc_csc_cpr_regval()
1485 regval[2] = CVAL(csc->m[CSC_GG], csc->m[CSC_GB]); in dispc_csc_cpr_regval()
1486 regval[3] = CVAL(csc->m[CSC_BR], csc->m[CSC_BG]); in dispc_csc_cpr_regval()
1487 regval[4] = CVAL(csc->m[CSC_BB], 0); in dispc_csc_cpr_regval()
1506 csc->to_regval(csc, regval); in dispc_k2g_vid_write_csc()
1509 dev_warn(dispc->dev, "%s: No post offset support for %s\n", in dispc_k2g_vid_write_csc()
1510 __func__, csc->name); in dispc_k2g_vid_write_csc()
1529 csc->to_regval(csc, regval); in dispc_k3_vid_write_csc()
1536 /* YUV -> RGB, ITU-R BT.601, full range */
1540 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/
1542 { 0, -2048, -2048, }, /* full range */
1548 /* YUV -> RGB, ITU-R BT.601, limited range */
1552 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/
1554 { -256, -2048, -2048, }, /* limited range */
1560 /* YUV -> RGB, ITU-R BT.709, full range */
1564 256, -48, -120, /* gy, gcb, gcr |1.000 -0.187 -0.467|*/
1566 { 0, -2048, -2048, }, /* full range */
1572 /* YUV -> RGB, ITU-R BT.709, limited range */
1576 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/
1578 { -256, -2048, -2048, }, /* limited range */
1617 const struct dispc_csc_coef *coef; in dispc_vid_csc_setup() local
1619 coef = dispc_find_csc(state->color_encoding, state->color_range); in dispc_vid_csc_setup()
1620 if (!coef) { in dispc_vid_csc_setup()
1621 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n", in dispc_vid_csc_setup()
1622 __func__, state->color_encoding, state->color_range); in dispc_vid_csc_setup()
1626 if (dispc->feat->subrev == DISPC_K2G) in dispc_vid_csc_setup()
1627 dispc_k2g_vid_write_csc(dispc, hw_plane, coef); in dispc_vid_csc_setup()
1629 dispc_k3_vid_write_csc(dispc, hw_plane, coef); in dispc_vid_csc_setup()
1676 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__); in dispc_vid_write_fir_coefs()
1682 u16 c0 = coefs->c0[phase]; in dispc_vid_write_fir_coefs()
1692 c1 = coefs->c1[phase]; in dispc_vid_write_fir_coefs()
1693 c2 = coefs->c2[phase]; in dispc_vid_write_fir_coefs()
1726 const struct dispc_features_scaling *f = &dispc->feat->scaling; in dispc_vid_calc_scaling()
1727 u32 fourcc = state->fb->format->format; in dispc_vid_calc_scaling()
1728 u32 in_width_max_5tap = f->in_width_max_5tap_rgb; in dispc_vid_calc_scaling()
1729 u32 in_width_max_3tap = f->in_width_max_3tap_rgb; in dispc_vid_calc_scaling()
1734 sp->xinc = 1; in dispc_vid_calc_scaling()
1735 sp->yinc = 1; in dispc_vid_calc_scaling()
1736 sp->in_w = state->src_w >> 16; in dispc_vid_calc_scaling()
1737 sp->in_w_uv = sp->in_w; in dispc_vid_calc_scaling()
1738 sp->in_h = state->src_h >> 16; in dispc_vid_calc_scaling()
1739 sp->in_h_uv = sp->in_h; in dispc_vid_calc_scaling()
1741 sp->scale_x = sp->in_w != state->crtc_w; in dispc_vid_calc_scaling()
1742 sp->scale_y = sp->in_h != state->crtc_h; in dispc_vid_calc_scaling()
1745 in_width_max_5tap = f->in_width_max_5tap_yuv; in dispc_vid_calc_scaling()
1746 in_width_max_3tap = f->in_width_max_3tap_yuv; in dispc_vid_calc_scaling()
1748 sp->in_w_uv >>= 1; in dispc_vid_calc_scaling()
1749 sp->scale_x = true; in dispc_vid_calc_scaling()
1752 sp->in_h_uv >>= 1; in dispc_vid_calc_scaling()
1753 sp->scale_y = true; in dispc_vid_calc_scaling()
1758 if ((!sp->scale_x && !sp->scale_y) || lite_plane) in dispc_vid_calc_scaling()
1761 if (sp->in_w > in_width_max_5tap) { in dispc_vid_calc_scaling()
1762 sp->five_taps = false; in dispc_vid_calc_scaling()
1764 downscale_limit = f->downscale_limit_3tap; in dispc_vid_calc_scaling()
1766 sp->five_taps = true; in dispc_vid_calc_scaling()
1768 downscale_limit = f->downscale_limit_5tap; in dispc_vid_calc_scaling()
1771 if (sp->scale_x) { in dispc_vid_calc_scaling()
1772 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); in dispc_vid_calc_scaling()
1774 if (sp->fir_xinc < dispc_calc_fir_inc(1, f->upscale_limit)) { in dispc_vid_calc_scaling()
1775 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1776 "%s: X-scaling factor %u/%u > %u\n", in dispc_vid_calc_scaling()
1777 __func__, state->crtc_w, state->src_w >> 16, in dispc_vid_calc_scaling()
1778 f->upscale_limit); in dispc_vid_calc_scaling()
1779 return -EINVAL; in dispc_vid_calc_scaling()
1782 if (sp->fir_xinc >= dispc_calc_fir_inc(downscale_limit, 1)) { in dispc_vid_calc_scaling()
1783 sp->xinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_w, in dispc_vid_calc_scaling()
1784 state->crtc_w), in dispc_vid_calc_scaling()
1787 if (sp->xinc > f->xinc_max) { in dispc_vid_calc_scaling()
1788 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1789 "%s: X-scaling factor %u/%u < 1/%u\n", in dispc_vid_calc_scaling()
1790 __func__, state->crtc_w, in dispc_vid_calc_scaling()
1791 state->src_w >> 16, in dispc_vid_calc_scaling()
1792 downscale_limit * f->xinc_max); in dispc_vid_calc_scaling()
1793 return -EINVAL; in dispc_vid_calc_scaling()
1796 sp->in_w = (state->src_w >> 16) / sp->xinc; in dispc_vid_calc_scaling()
1799 while (sp->in_w > in_width_max) { in dispc_vid_calc_scaling()
1800 sp->xinc++; in dispc_vid_calc_scaling()
1801 sp->in_w = (state->src_w >> 16) / sp->xinc; in dispc_vid_calc_scaling()
1804 if (sp->xinc > f->xinc_max) { in dispc_vid_calc_scaling()
1805 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1807 state->src_w >> 16, in_width_max * f->xinc_max); in dispc_vid_calc_scaling()
1808 return -EINVAL; in dispc_vid_calc_scaling()
1817 sp->in_w &= ~1; in dispc_vid_calc_scaling()
1819 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); in dispc_vid_calc_scaling()
1822 if (sp->scale_y) { in dispc_vid_calc_scaling()
1823 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, state->crtc_h); in dispc_vid_calc_scaling()
1825 if (sp->fir_yinc < dispc_calc_fir_inc(1, f->upscale_limit)) { in dispc_vid_calc_scaling()
1826 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1827 "%s: Y-scaling factor %u/%u > %u\n", in dispc_vid_calc_scaling()
1828 __func__, state->crtc_h, state->src_h >> 16, in dispc_vid_calc_scaling()
1829 f->upscale_limit); in dispc_vid_calc_scaling()
1830 return -EINVAL; in dispc_vid_calc_scaling()
1833 if (sp->fir_yinc >= dispc_calc_fir_inc(downscale_limit, 1)) { in dispc_vid_calc_scaling()
1834 sp->yinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_h, in dispc_vid_calc_scaling()
1835 state->crtc_h), in dispc_vid_calc_scaling()
1838 sp->in_h /= sp->yinc; in dispc_vid_calc_scaling()
1839 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, in dispc_vid_calc_scaling()
1840 state->crtc_h); in dispc_vid_calc_scaling()
1844 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1845 "%s: %ux%u decim %ux%u -> %ux%u firinc %u.%03ux%u.%03u taps %u -> %ux%u\n", in dispc_vid_calc_scaling()
1846 __func__, state->src_w >> 16, state->src_h >> 16, in dispc_vid_calc_scaling()
1847 sp->xinc, sp->yinc, sp->in_w, sp->in_h, in dispc_vid_calc_scaling()
1848 sp->fir_xinc / 0x200000u, in dispc_vid_calc_scaling()
1849 ((sp->fir_xinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, in dispc_vid_calc_scaling()
1850 sp->fir_yinc / 0x200000u, in dispc_vid_calc_scaling()
1851 ((sp->fir_yinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, in dispc_vid_calc_scaling()
1852 sp->five_taps ? 5 : 3, in dispc_vid_calc_scaling()
1853 state->crtc_w, state->crtc_h); in dispc_vid_calc_scaling()
1856 if (sp->scale_x) { in dispc_vid_calc_scaling()
1857 sp->in_w_uv /= sp->xinc; in dispc_vid_calc_scaling()
1858 sp->fir_xinc_uv = dispc_calc_fir_inc(sp->in_w_uv, in dispc_vid_calc_scaling()
1859 state->crtc_w); in dispc_vid_calc_scaling()
1860 sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1861 sp->fir_xinc_uv, in dispc_vid_calc_scaling()
1864 if (sp->scale_y) { in dispc_vid_calc_scaling()
1865 sp->in_h_uv /= sp->yinc; in dispc_vid_calc_scaling()
1866 sp->fir_yinc_uv = dispc_calc_fir_inc(sp->in_h_uv, in dispc_vid_calc_scaling()
1867 state->crtc_h); in dispc_vid_calc_scaling()
1868 sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1869 sp->fir_yinc_uv, in dispc_vid_calc_scaling()
1870 sp->five_taps); in dispc_vid_calc_scaling()
1874 if (sp->scale_x) in dispc_vid_calc_scaling()
1875 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc, in dispc_vid_calc_scaling()
1878 if (sp->scale_y) in dispc_vid_calc_scaling()
1879 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc, in dispc_vid_calc_scaling()
1880 sp->five_taps); in dispc_vid_calc_scaling()
1892 sp->scale_x, 7, 7); in dispc_vid_set_scaling()
1896 sp->scale_y, 8, 8); in dispc_vid_set_scaling()
1899 if (!sp->scale_x && !sp->scale_y) in dispc_vid_set_scaling()
1902 /* VERTICAL 5-TAPS */ in dispc_vid_set_scaling()
1904 sp->five_taps, 21, 21); in dispc_vid_set_scaling()
1907 if (sp->scale_x) { in dispc_vid_set_scaling()
1909 sp->fir_xinc_uv); in dispc_vid_set_scaling()
1912 sp->xcoef_uv); in dispc_vid_set_scaling()
1914 if (sp->scale_y) { in dispc_vid_set_scaling()
1916 sp->fir_yinc_uv); in dispc_vid_set_scaling()
1919 sp->ycoef_uv); in dispc_vid_set_scaling()
1923 if (sp->scale_x) { in dispc_vid_set_scaling()
1924 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc); in dispc_vid_set_scaling()
1927 sp->xcoef); in dispc_vid_set_scaling()
1930 if (sp->scale_y) { in dispc_vid_set_scaling()
1931 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc); in dispc_vid_set_scaling()
1933 DISPC_VID_FIR_COEF_VERT, sp->ycoef); in dispc_vid_set_scaling()
2004 WARN_ON(!dispc->fourccs); in dispc_plane_formats()
2006 *len = dispc->num_fourccs; in dispc_plane_formats()
2008 return dispc->fourccs; in dispc_plane_formats()
2016 return 1 + (pixels - 1) * ps; in pixinc()
2018 return 1 - (-pixels + 1) * ps; in pixinc()
2028 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_check()
2029 u32 fourcc = state->fb->format->format; in dispc_plane_check()
2030 bool need_scaling = state->src_w >> 16 != state->crtc_w || in dispc_plane_check()
2031 state->src_h >> 16 != state->crtc_h; in dispc_plane_check()
2036 if (!dispc_find_csc(state->color_encoding, in dispc_plane_check()
2037 state->color_range)) { in dispc_plane_check()
2038 dev_dbg(dispc->dev, in dispc_plane_check()
2040 __func__, state->color_encoding, in dispc_plane_check()
2041 state->color_range, hw_plane); in dispc_plane_check()
2042 return -EINVAL; in dispc_plane_check()
2048 dev_dbg(dispc->dev, in dispc_plane_check()
2051 state->src_w >> 16, state->src_h >> 16, in dispc_plane_check()
2052 state->crtc_w, state->crtc_h); in dispc_plane_check()
2053 return -EINVAL; in dispc_plane_check()
2066 struct drm_framebuffer *fb = state->fb; in dispc_plane_state_dma_addr()
2068 u32 x = state->src_x >> 16; in dispc_plane_state_dma_addr()
2069 u32 y = state->src_y >> 16; in dispc_plane_state_dma_addr()
2071 gem = drm_fb_dma_get_gem_obj(state->fb, 0); in dispc_plane_state_dma_addr()
2073 return gem->dma_addr + fb->offsets[0] + x * fb->format->cpp[0] + in dispc_plane_state_dma_addr()
2074 y * fb->pitches[0]; in dispc_plane_state_dma_addr()
2080 struct drm_framebuffer *fb = state->fb; in dispc_plane_state_p_uv_addr()
2082 u32 x = state->src_x >> 16; in dispc_plane_state_p_uv_addr()
2083 u32 y = state->src_y >> 16; in dispc_plane_state_p_uv_addr()
2085 if (WARN_ON(state->fb->format->num_planes != 2)) in dispc_plane_state_p_uv_addr()
2090 return gem->dma_addr + fb->offsets[1] + in dispc_plane_state_p_uv_addr()
2091 (x * fb->format->cpp[1] / fb->format->hsub) + in dispc_plane_state_p_uv_addr()
2092 (y * fb->pitches[1] / fb->format->vsub); in dispc_plane_state_p_uv_addr()
2099 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_setup()
2100 u32 fourcc = state->fb->format->format; in dispc_plane_setup()
2101 u16 cpp = state->fb->format->cpp[0]; in dispc_plane_setup()
2102 u32 fb_width = state->fb->pitches[0] / cpp; in dispc_plane_setup()
2116 (scale.in_w - 1) | ((scale.in_h - 1) << 16)); in dispc_plane_setup()
2127 pixinc(1 + (scale.yinc * fb_width - in dispc_plane_setup()
2131 if (state->fb->format->num_planes == 2) { in dispc_plane_setup()
2132 u16 cpp_uv = state->fb->format->cpp[1]; in dispc_plane_setup()
2133 u32 fb_width_uv = state->fb->pitches[1] / cpp_uv; in dispc_plane_setup()
2146 pixinc(1 + (scale.yinc * fb_width_uv - in dispc_plane_setup()
2153 (state->crtc_w - 1) | in dispc_plane_setup()
2154 ((state->crtc_h - 1) << 16)); in dispc_plane_setup()
2159 /* enable YUV->RGB color conversion */ in dispc_plane_setup()
2168 0xFF & (state->alpha >> 8)); in dispc_plane_setup()
2170 if (state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) in dispc_plane_setup()
2206 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k2g_plane_init()
2213 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k2g_plane_init()
2219 thr_high = size - 1; in dispc_k2g_plane_init()
2227 dev_dbg(dispc->dev, in dispc_k2g_plane_init()
2229 dispc->feat->vid_name[hw_plane], in dispc_k2g_plane_init()
2243 * Prefetch up to fifo high-threshold value to minimize the in dispc_k2g_plane_init()
2258 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k3_plane_init()
2268 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k3_plane_init()
2274 thr_high = size - 1; in dispc_k3_plane_init()
2282 dev_dbg(dispc->dev, in dispc_k3_plane_init()
2284 dispc->feat->vid_name[hw_plane], in dispc_k3_plane_init()
2305 switch (dispc->feat->subrev) { in dispc_plane_init()
2324 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_vp_init()
2326 /* Enable the gamma Shadow bit-field for all VPs*/ in dispc_vp_init()
2327 for (i = 0; i < dispc->feat->num_vps; i++) in dispc_vp_init()
2337 if (dispc->feat->subrev == DISPC_J721E) { in dispc_initial_config()
2348 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_k2g_vp_write_gamma_table()
2349 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_k2g_vp_write_gamma_table()
2352 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_k2g_vp_write_gamma_table()
2354 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_k2g_vp_write_gamma_table()
2370 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_am65x_vp_write_gamma_table()
2371 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_am65x_vp_write_gamma_table()
2374 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_am65x_vp_write_gamma_table()
2376 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_am65x_vp_write_gamma_table()
2391 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_j721e_vp_write_gamma_table()
2392 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_j721e_vp_write_gamma_table()
2395 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_j721e_vp_write_gamma_table()
2397 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT)) in dispc_j721e_vp_write_gamma_table()
2413 switch (dispc->feat->subrev) { in dispc_vp_write_gamma_table()
2441 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_vp_set_gamma()
2442 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_vp_set_gamma()
2446 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n", in dispc_vp_set_gamma()
2449 if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT) in dispc_vp_set_gamma()
2459 for (i = 0; i < length - 1; ++i) { in dispc_vp_set_gamma()
2460 unsigned int first = i * (hwlen - 1) / (length - 1); in dispc_vp_set_gamma()
2461 unsigned int last = (i + 1) * (hwlen - 1) / (length - 1); in dispc_vp_set_gamma()
2462 unsigned int w = last - first; in dispc_vp_set_gamma()
2470 r = (lut[i].red * (w - j) + lut[i + 1].red * j) / w; in dispc_vp_set_gamma()
2471 g = (lut[i].green * (w - j) + lut[i + 1].green * j) / w; in dispc_vp_set_gamma()
2472 b = (lut[i].blue * (w - j) + lut[i + 1].blue * j) / w; in dispc_vp_set_gamma()
2474 r >>= 16 - hwbits; in dispc_vp_set_gamma()
2475 g >>= 16 - hwbits; in dispc_vp_set_gamma()
2476 b >>= 16 - hwbits; in dispc_vp_set_gamma()
2486 static s16 dispc_S31_32_to_s2_8(s64 coef) in dispc_S31_32_to_s2_8() argument
2489 u64 cbits = (u64)coef; in dispc_S31_32_to_s2_8()
2493 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x200); in dispc_S31_32_to_s2_8()
2505 cpr->to_regval = dispc_csc_cpr_regval; in dispc_k2g_cpr_from_ctm()
2506 cpr->m[CSC_RR] = dispc_S31_32_to_s2_8(ctm->matrix[0]); in dispc_k2g_cpr_from_ctm()
2507 cpr->m[CSC_RG] = dispc_S31_32_to_s2_8(ctm->matrix[1]); in dispc_k2g_cpr_from_ctm()
2508 cpr->m[CSC_RB] = dispc_S31_32_to_s2_8(ctm->matrix[2]); in dispc_k2g_cpr_from_ctm()
2509 cpr->m[CSC_GR] = dispc_S31_32_to_s2_8(ctm->matrix[3]); in dispc_k2g_cpr_from_ctm()
2510 cpr->m[CSC_GG] = dispc_S31_32_to_s2_8(ctm->matrix[4]); in dispc_k2g_cpr_from_ctm()
2511 cpr->m[CSC_GB] = dispc_S31_32_to_s2_8(ctm->matrix[5]); in dispc_k2g_cpr_from_ctm()
2512 cpr->m[CSC_BR] = dispc_S31_32_to_s2_8(ctm->matrix[6]); in dispc_k2g_cpr_from_ctm()
2513 cpr->m[CSC_BG] = dispc_S31_32_to_s2_8(ctm->matrix[7]); in dispc_k2g_cpr_from_ctm()
2514 cpr->m[CSC_BB] = dispc_S31_32_to_s2_8(ctm->matrix[8]); in dispc_k2g_cpr_from_ctm()
2523 regval[0] = CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]); in dispc_k2g_vp_csc_cpr_regval()
2524 regval[1] = CVAL(csc->m[CSC_GB], csc->m[CSC_GG], csc->m[CSC_GR]); in dispc_k2g_vp_csc_cpr_regval()
2525 regval[2] = CVAL(csc->m[CSC_RB], csc->m[CSC_RG], csc->m[CSC_RR]); in dispc_k2g_vp_csc_cpr_regval()
2564 static s16 dispc_S31_32_to_s3_8(s64 coef) in dispc_S31_32_to_s3_8() argument
2567 u64 cbits = (u64)coef; in dispc_S31_32_to_s3_8()
2571 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x400); in dispc_S31_32_to_s3_8()
2583 cpr->to_regval = dispc_csc_cpr_regval; in dispc_csc_from_ctm()
2584 cpr->m[CSC_RR] = dispc_S31_32_to_s3_8(ctm->matrix[0]); in dispc_csc_from_ctm()
2585 cpr->m[CSC_RG] = dispc_S31_32_to_s3_8(ctm->matrix[1]); in dispc_csc_from_ctm()
2586 cpr->m[CSC_RB] = dispc_S31_32_to_s3_8(ctm->matrix[2]); in dispc_csc_from_ctm()
2587 cpr->m[CSC_GR] = dispc_S31_32_to_s3_8(ctm->matrix[3]); in dispc_csc_from_ctm()
2588 cpr->m[CSC_GG] = dispc_S31_32_to_s3_8(ctm->matrix[4]); in dispc_csc_from_ctm()
2589 cpr->m[CSC_GB] = dispc_S31_32_to_s3_8(ctm->matrix[5]); in dispc_csc_from_ctm()
2590 cpr->m[CSC_BR] = dispc_S31_32_to_s3_8(ctm->matrix[6]); in dispc_csc_from_ctm()
2591 cpr->m[CSC_BG] = dispc_S31_32_to_s3_8(ctm->matrix[7]); in dispc_csc_from_ctm()
2592 cpr->m[CSC_BB] = dispc_S31_32_to_s3_8(ctm->matrix[8]); in dispc_csc_from_ctm()
2606 csc->to_regval(csc, regval); in dispc_k3_vp_write_csc()
2639 if (!(state->color_mgmt_changed || newmodeset)) in dispc_vp_set_color_mgmt()
2642 if (state->gamma_lut) { in dispc_vp_set_color_mgmt()
2643 lut = (struct drm_color_lut *)state->gamma_lut->data; in dispc_vp_set_color_mgmt()
2644 length = state->gamma_lut->length / sizeof(*lut); in dispc_vp_set_color_mgmt()
2649 if (state->ctm) in dispc_vp_set_color_mgmt()
2650 ctm = (struct drm_color_ctm *)state->ctm->data; in dispc_vp_set_color_mgmt()
2652 if (dispc->feat->subrev == DISPC_K2G) in dispc_vp_set_color_mgmt()
2667 dev_dbg(dispc->dev, "suspend\n"); in dispc_runtime_suspend()
2669 dispc->is_enabled = false; in dispc_runtime_suspend()
2671 clk_disable_unprepare(dispc->fclk); in dispc_runtime_suspend()
2678 dev_dbg(dispc->dev, "resume\n"); in dispc_runtime_resume()
2680 clk_prepare_enable(dispc->fclk); in dispc_runtime_resume()
2683 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); in dispc_runtime_resume()
2685 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", in dispc_runtime_resume()
2688 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2693 if (dispc->feat->subrev == DISPC_AM625 || in dispc_runtime_resume()
2694 dispc->feat->subrev == DISPC_AM65X) in dispc_runtime_resume()
2695 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2700 dev_dbg(dispc->dev, "DISPC IDLE %d\n", in dispc_runtime_resume()
2705 dispc->is_enabled = true; in dispc_runtime_resume()
2707 tidss_irq_resume(dispc->tidss); in dispc_runtime_resume()
2714 dev_dbg(tidss->dev, "%s\n", __func__); in dispc_remove()
2716 tidss->dispc = NULL; in dispc_remove()
2726 dev_err(&pdev->dev, "cannot ioremap resource '%s'\n", name); in dispc_iomap_resource()
2738 dispc->oldi_io_ctrl = in dispc_init_am65x_oldi_io_ctrl()
2739 syscon_regmap_lookup_by_phandle(dev->of_node, in dispc_init_am65x_oldi_io_ctrl()
2740 "ti,am65x-oldi-io-ctrl"); in dispc_init_am65x_oldi_io_ctrl()
2741 if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) { in dispc_init_am65x_oldi_io_ctrl()
2742 dispc->oldi_io_ctrl = NULL; in dispc_init_am65x_oldi_io_ctrl()
2743 } else if (IS_ERR(dispc->oldi_io_ctrl)) { in dispc_init_am65x_oldi_io_ctrl()
2745 __func__, PTR_ERR(dispc->oldi_io_ctrl)); in dispc_init_am65x_oldi_io_ctrl()
2746 return PTR_ERR(dispc->oldi_io_ctrl); in dispc_init_am65x_oldi_io_ctrl()
2759 dispc->errata.i2000 = true; in dispc_init_errata()
2760 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n"); in dispc_init_errata()
2773 for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx) in dispc_softreset_k2g()
2782 if (dispc->feat->subrev == DISPC_K2G) { in dispc_softreset()
2790 ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, in dispc_softreset()
2793 dev_err(dispc->dev, "failed to reset dispc\n"); in dispc_softreset()
2802 struct device *dev = dispc->dev; in dispc_init_hw()
2811 ret = clk_prepare_enable(dispc->fclk); in dispc_init_hw()
2821 clk_disable_unprepare(dispc->fclk); in dispc_init_hw()
2831 clk_disable_unprepare(dispc->fclk); in dispc_init_hw()
2845 struct device *dev = tidss->dev; in dispc_init()
2854 feat = tidss->feat; in dispc_init()
2856 if (feat->subrev != DISPC_K2G) { in dispc_init()
2859 dev_warn(dev, "cannot set DMA masks to 48-bit\n"); in dispc_init()
2866 return -ENOMEM; in dispc_init()
2868 dispc->tidss = tidss; in dispc_init()
2869 dispc->dev = dev; in dispc_init()
2870 dispc->feat = feat; in dispc_init()
2874 dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats), in dispc_init()
2875 sizeof(*dispc->fourccs), GFP_KERNEL); in dispc_init()
2876 if (!dispc->fourccs) in dispc_init()
2877 return -ENOMEM; in dispc_init()
2881 if (dispc->errata.i2000 && in dispc_init()
2885 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc; in dispc_init()
2888 dispc->num_fourccs = num_fourccs; in dispc_init()
2890 dispc_common_regmap = dispc->feat->common_regs; in dispc_init()
2892 r = dispc_iomap_resource(pdev, dispc->feat->common, in dispc_init()
2893 &dispc->base_common); in dispc_init()
2897 for (i = 0; i < dispc->feat->num_planes; i++) { in dispc_init()
2898 r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i], in dispc_init()
2899 &dispc->base_vid[i]); in dispc_init()
2904 for (i = 0; i < dispc->feat->num_vps; i++) { in dispc_init()
2905 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; in dispc_init()
2909 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i], in dispc_init()
2910 &dispc->base_ovr[i]); in dispc_init()
2914 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i], in dispc_init()
2915 &dispc->base_vp[i]); in dispc_init()
2919 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]); in dispc_init()
2922 dispc->feat->vpclk_name[i], PTR_ERR(clk)); in dispc_init()
2925 dispc->vp_clk[i] = clk; in dispc_init()
2931 return -ENOMEM; in dispc_init()
2932 dispc->vp_data[i].gamma_table = gamma_table; in dispc_init()
2935 if (feat->subrev == DISPC_AM65X) { in dispc_init()
2941 dispc->fclk = devm_clk_get(dev, "fck"); in dispc_init()
2942 if (IS_ERR(dispc->fclk)) { in dispc_init()
2944 __func__, PTR_ERR(dispc->fclk)); in dispc_init()
2945 return PTR_ERR(dispc->fclk); in dispc_init()
2947 dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk)); in dispc_init()
2949 of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", in dispc_init()
2950 &dispc->memory_bandwidth_limit); in dispc_init()
2956 tidss->dispc = dispc; in dispc_init()