Lines Matching +full:1 +full:x
14 #define SOR_SUPER_STATE_ATTACHED (1 << 3)
15 #define SOR_SUPER_STATE_MODE_NORMAL (1 << 2)
18 #define SOR_SUPER_STATE_HEAD_MODE_SNOOZE (1 << 0)
30 #define SOR_STATE_ASY_VSYNCPOL (1 << 13)
31 #define SOR_STATE_ASY_HSYNCPOL (1 << 12)
44 #define SOR_STATE_ASY_OWNER(x) (((x) & 0xf) << 0) argument
46 #define SOR_HEAD_STATE0(x) (0x05 + (x)) argument
50 #define SOR_HEAD_STATE_DYNRANGE_CEA (1 << 2)
53 #define SOR_HEAD_STATE1(x) (0x07 + (x)) argument
54 #define SOR_HEAD_STATE2(x) (0x09 + (x)) argument
55 #define SOR_HEAD_STATE3(x) (0x0b + (x)) argument
56 #define SOR_HEAD_STATE4(x) (0x0d + (x)) argument
57 #define SOR_HEAD_STATE5(x) (0x0f + (x)) argument
59 #define SOR_CRC_CNTRL_ENABLE (1 << 0)
64 #define SOR_CLK_CNTRL_DP_LINK_SPEED(x) (((x) & 0x1f) << 2) argument
70 #define SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK (1 << 0)
77 #define SOR_PWR_TRIGGER (1 << 31)
78 #define SOR_PWR_MODE_SAFE (1 << 28)
79 #define SOR_PWR_NORMAL_STATE_PU (1 << 0)
82 #define SOR_TEST_CRC_POST_SERIALIZE (1 << 23)
83 #define SOR_TEST_ATTACHED (1 << 10)
89 #define SOR_PLL0_ICHPMP(x) (((x) & 0xf) << 24) argument
91 #define SOR_PLL0_FILTER(x) (((x) & 0xf) << 16) argument
93 #define SOR_PLL0_VCOCAP(x) (((x) & 0xf) << 8) argument
96 #define SOR_PLL0_PLLREG_LEVEL(x) (((x) & 0x3) << 6) argument
98 #define SOR_PLL0_PLLREG_LEVEL_V15 SOR_PLL0_PLLREG_LEVEL(1)
101 #define SOR_PLL0_PULLDOWN (1 << 5)
102 #define SOR_PLL0_RESISTOR_EXT (1 << 4)
103 #define SOR_PLL0_VCOPD (1 << 2)
104 #define SOR_PLL0_PWR (1 << 0)
109 #define SOR_PLL1_LOADADJ(x) (((x) & 0xf) << 20) argument
110 #define SOR_PLL1_TERM_COMPOUT (1 << 15)
112 #define SOR_PLL1_TMDS_TERMADJ(x) (((x) & 0xf) << 9) argument
113 #define SOR_PLL1_TMDS_TERM (1 << 8)
116 #define SOR_PLL2_LVDS_ENABLE (1 << 25)
117 #define SOR_PLL2_SEQ_PLLCAPPD_ENFORCE (1 << 24)
118 #define SOR_PLL2_PORT_POWERDOWN (1 << 23)
119 #define SOR_PLL2_BANDGAP_POWERDOWN (1 << 22)
120 #define SOR_PLL2_POWERDOWN_OVERRIDE (1 << 18)
121 #define SOR_PLL2_SEQ_PLLCAPPD (1 << 17)
122 #define SOR_PLL2_SEQ_PLL_PULLDOWN (1 << 16)
126 #define SOR_PLL3_BG_TEMP_COEF(x) (((x) & 0xf) << 28) argument
128 #define SOR_PLL3_BG_VREF_LEVEL(x) (((x) & 0xf) << 24) argument
130 #define SOR_PLL3_PLL_VDD_MODE_3V3 (1 << 13)
132 #define SOR_PLL3_AVDD10_LEVEL(x) (((x) & 0xf) << 8) argument
134 #define SOR_PLL3_AVDD14_LEVEL(x) (((x) & 0xf) << 4) argument
138 #define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24) argument
139 #define SOR_CSTM_LVDS (1 << 16)
140 #define SOR_CSTM_LINK_ACT_B (1 << 15)
141 #define SOR_CSTM_LINK_ACT_A (1 << 14)
142 #define SOR_CSTM_UPPER (1 << 11)
146 #define SOR_CRCA_VALID (1 << 0)
147 #define SOR_CRCA_RESET (1 << 0)
151 #define SOR_SEQ_CTL_PD_PC_ALT(x) (((x) & 0xf) << 12) argument
152 #define SOR_SEQ_CTL_PD_PC(x) (((x) & 0xf) << 8) argument
153 #define SOR_SEQ_CTL_PU_PC_ALT(x) (((x) & 0xf) << 4) argument
154 #define SOR_SEQ_CTL_PU_PC(x) (((x) & 0xf) << 0) argument
157 #define SOR_LANE_SEQ_CTL_TRIGGER (1 << 31)
158 #define SOR_LANE_SEQ_CTL_STATE_BUSY (1 << 28)
160 #define SOR_LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20)
162 #define SOR_LANE_SEQ_CTL_POWER_STATE_DOWN (1 << 16)
163 #define SOR_LANE_SEQ_CTL_DELAY(x) (((x) & 0xf) << 12) argument
165 #define SOR_SEQ_INST(x) (0x22 + (x)) argument
166 #define SOR_SEQ_INST_PLL_PULLDOWN (1 << 31)
167 #define SOR_SEQ_INST_POWERDOWN_MACRO (1 << 30)
168 #define SOR_SEQ_INST_ASSERT_PLL_RESET (1 << 29)
169 #define SOR_SEQ_INST_BLANK_V (1 << 28)
170 #define SOR_SEQ_INST_BLANK_H (1 << 27)
171 #define SOR_SEQ_INST_BLANK_DE (1 << 26)
172 #define SOR_SEQ_INST_BLACK_DATA (1 << 25)
173 #define SOR_SEQ_INST_TRISTATE_IOS (1 << 24)
174 #define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
176 #define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
178 #define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
180 #define SOR_SEQ_INST_SEQUENCE_DOWN (1 << 19)
182 #define SOR_SEQ_INST_LANE_SEQ_RUN (1 << 18)
183 #define SOR_SEQ_INST_PORT_POWERDOWN (1 << 17)
184 #define SOR_SEQ_INST_PLL_POWERDOWN (1 << 16)
185 #define SOR_SEQ_INST_HALT (1 << 15)
187 #define SOR_SEQ_INST_WAIT_MS (1 << 12)
189 #define SOR_SEQ_INST_WAIT(x) (((x) & 0x3ff) << 0) argument
195 #define SOR_PWM_CTL_TRIGGER (1 << 31)
196 #define SOR_PWM_CTL_CLK_SEL (1 << 30)
224 #define SOR_XBAR_CTRL_LINK_SWAP (1 << 1)
225 #define SOR_XBAR_CTRL_BYPASS (1 << 0)
230 #define SOR_DP_LINKCTL_LANE_COUNT(x) (((1 << (x)) - 1) << 16) argument
231 #define SOR_DP_LINKCTL_ENHANCED_FRAME (1 << 14)
233 #define SOR_DP_LINKCTL_TU_SIZE(x) (((x) & 0x7f) << 2) argument
234 #define SOR_DP_LINKCTL_ENABLE (1 << 0)
242 #define SOR_LANE_DRIVE_CURRENT_LANE3(x) (((x) & 0xff) << 24) argument
243 #define SOR_LANE_DRIVE_CURRENT_LANE2(x) (((x) & 0xff) << 16) argument
244 #define SOR_LANE_DRIVE_CURRENT_LANE1(x) (((x) & 0xff) << 8) argument
245 #define SOR_LANE_DRIVE_CURRENT_LANE0(x) (((x) & 0xff) << 0) argument
251 #define SOR_LANE_PREEMPHASIS_LANE3(x) (((x) & 0xff) << 24) argument
252 #define SOR_LANE_PREEMPHASIS_LANE2(x) (((x) & 0xff) << 16) argument
253 #define SOR_LANE_PREEMPHASIS_LANE1(x) (((x) & 0xff) << 8) argument
254 #define SOR_LANE_PREEMPHASIS_LANE0(x) (((x) & 0xff) << 0) argument
258 #define SOR_LANE_POSTCURSOR_LANE3(x) (((x) & 0xff) << 24) argument
259 #define SOR_LANE_POSTCURSOR_LANE2(x) (((x) & 0xff) << 16) argument
260 #define SOR_LANE_POSTCURSOR_LANE1(x) (((x) & 0xff) << 8) argument
261 #define SOR_LANE_POSTCURSOR_LANE0(x) (((x) & 0xff) << 0) argument
264 #define SOR_DP_CONFIG_DISPARITY_NEGATIVE (1 << 31)
265 #define SOR_DP_CONFIG_ACTIVE_SYM_ENABLE (1 << 26)
266 #define SOR_DP_CONFIG_ACTIVE_SYM_POLARITY (1 << 24)
268 #define SOR_DP_CONFIG_ACTIVE_SYM_FRAC(x) (((x) & 0xf) << 16) argument
270 #define SOR_DP_CONFIG_ACTIVE_SYM_COUNT(x) (((x) & 0x7f) << 8) argument
272 #define SOR_DP_CONFIG_WATERMARK(x) (((x) & 0x3f) << 0) argument
279 #define SOR_DP_PADCTL_PAD_CAL_PD (1 << 23)
280 #define SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22)
282 #define SOR_DP_PADCTL_TX_PU(x) (((x) & 0xff) << 8) argument
283 #define SOR_DP_PADCTL_CM_TXD_3 (1 << 7)
284 #define SOR_DP_PADCTL_CM_TXD_2 (1 << 6)
285 #define SOR_DP_PADCTL_CM_TXD_1 (1 << 5)
286 #define SOR_DP_PADCTL_CM_TXD_0 (1 << 4)
287 #define SOR_DP_PADCTL_CM_TXD(x) (1 << (4 + (x))) argument
288 #define SOR_DP_PADCTL_PD_TXD_3 (1 << 3)
289 #define SOR_DP_PADCTL_PD_TXD_0 (1 << 2)
290 #define SOR_DP_PADCTL_PD_TXD_1 (1 << 1)
291 #define SOR_DP_PADCTL_PD_TXD_2 (1 << 0)
292 #define SOR_DP_PADCTL_PD_TXD(x) (1 << (0 + (x))) argument
300 #define SOR_DP_SPARE_DISP_VIDEO_PREAMBLE (1 << 3)
301 #define SOR_DP_SPARE_MACRO_SOR_CLK (1 << 2)
302 #define SOR_DP_SPARE_PANEL_INTERNAL (1 << 1)
303 #define SOR_DP_SPARE_SEQ_ENABLE (1 << 0)
324 #define SOR_DP_TPG_CHANNEL_CODING (1 << 6)
327 #define SOR_DP_TPG_SCRAMBLER_GALIOS (1 << 4)
347 #define SOR_DP_PADCTL_SPAREPLL(x) (((x) & 0xff) << 24) argument
354 #define INFOFRAME_CTRL_CHECKSUM_ENABLE (1 << 9)
355 #define INFOFRAME_CTRL_SINGLE (1 << 8)
356 #define INFOFRAME_CTRL_OTHER (1 << 4)
357 #define INFOFRAME_CTRL_ENABLE (1 << 0)
360 #define INFOFRAME_STATUS_DONE (1 << 0)
363 #define INFOFRAME_HEADER_LEN(x) (((x) & 0xff) << 16) argument
364 #define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8) argument
365 #define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0) argument
370 #define SOR_HDMI_ACR_SUBPACK_LOW_SB1(x) (((x) & 0xff) << 24) argument
373 #define SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE (1 << 31)
379 #define SOR_HDMI_CTRL_ENABLE (1 << 30)
380 #define SOR_HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16) argument
381 #define SOR_HDMI_CTRL_AUDIO_LAYOUT (1 << 10)
382 #define SOR_HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0) argument
385 #define SOR_HDMI_SPARE_ACR_PRIORITY_HIGH (1 << 31)
386 #define SOR_HDMI_SPARE_CTS_RESET(x) (((x) & 0x7) << 16) argument
387 #define SOR_HDMI_SPARE_HW_CTS_ENABLE (1 << 0)
390 #define SOR_REFCLK_DIV_INT(x) ((((x) >> 2) & 0xff) << 8) argument
391 #define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x3) << 6) argument
394 #define SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED (1 << 1)
395 #define SOR_INPUT_CONTROL_HDMI_SRC_SELECT(x) (((x) & 0x1) << 0) argument
398 #define SOR_AUDIO_CNTRL_INJECT_NULLSMPL (1 << 29)
399 #define SOR_AUDIO_CNTRL_SOURCE_SELECT(x) (((x) & 0x3) << 20) argument
404 #define SOR_AUDIO_CNTRL_AFIFO_FLUSH (1 << 12)
407 #define SOR_AUDIO_SPARE_HBR_ENABLE (1 << 27)
418 #define SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID (1 << 30)
422 #define SOR_AUDIO_HDA_ELD_BUFWR_INDEX(x) (((x) & 0xff) << 8) argument
423 #define SOR_AUDIO_HDA_ELD_BUFWR_DATA(x) (((x) & 0xff) << 0) argument
426 #define SOR_AUDIO_HDA_PRESENSE_ELDV (1 << 1)
427 #define SOR_AUDIO_HDA_PRESENSE_PD (1 << 0)
438 #define SOR_INT_CODEC_CP_REQUEST (1 << 2)
439 #define SOR_INT_CODEC_SCRATCH1 (1 << 1)
440 #define SOR_INT_CODEC_SCRATCH0 (1 << 0)
450 #define SOR_HDMI_AUDIO_N_LOOKUP (1 << 28)
451 #define SOR_HDMI_AUDIO_N_RESET (1 << 20)
454 #define SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4 (1 << 1)
455 #define SOR_HDMI2_CTRL_SCRAMBLE (1 << 0)