Lines Matching refs:tegra_sor_writel
495 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() function
561 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
674 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
679 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
706 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
711 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
753 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
760 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
770 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
774 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
782 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
796 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
801 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
856 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_link_apply_training()
857 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_link_apply_training()
860 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_link_apply_training()
862 tegra_sor_writel(sor, pattern, SOR_DP_TPG); in tegra_sor_dp_link_apply_training()
868 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
889 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
898 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
920 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
930 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
958 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
959 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); in tegra_sor_super_update()
960 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
965 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
966 tegra_sor_writel(sor, 1, SOR_STATE0); in tegra_sor_update()
967 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
977 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
984 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
1007 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1013 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1055 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
1253 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1272 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1277 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1282 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1339 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1347 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1354 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1361 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1368 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1371 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); in tegra_sor_mode_set()
1381 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1398 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1404 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1431 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1455 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1461 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1466 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1508 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1512 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1516 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1522 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); in tegra_sor_show_crc()
1892 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
1904 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1909 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1927 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1948 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1958 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], in tegra_sor_write_eld()
1968 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR); in tegra_sor_write_eld()
1981 tegra_sor_writel(sor, value, SOR_INT_ENABLE); in tegra_sor_audio_prepare()
1982 tegra_sor_writel(sor, value, SOR_INT_MASK); in tegra_sor_audio_prepare()
1987 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_prepare()
1992 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_unprepare()
1993 tegra_sor_writel(sor, 0, SOR_INT_MASK); in tegra_sor_audio_unprepare()
1994 tegra_sor_writel(sor, 0, SOR_INT_ENABLE); in tegra_sor_audio_unprepare()
2015 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2018 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); in tegra_sor_audio_enable()
2047 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2058 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); in tegra_sor_hdmi_audio_enable()
2063 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); in tegra_sor_hdmi_audio_enable()
2067 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); in tegra_sor_hdmi_audio_enable()
2071 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); in tegra_sor_hdmi_audio_enable()
2075 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2078 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); in tegra_sor_hdmi_audio_enable()
2079 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320); in tegra_sor_hdmi_audio_enable()
2081 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441); in tegra_sor_hdmi_audio_enable()
2082 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441); in tegra_sor_hdmi_audio_enable()
2084 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882); in tegra_sor_hdmi_audio_enable()
2085 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882); in tegra_sor_hdmi_audio_enable()
2087 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764); in tegra_sor_hdmi_audio_enable()
2088 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764); in tegra_sor_hdmi_audio_enable()
2091 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); in tegra_sor_hdmi_audio_enable()
2092 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480); in tegra_sor_hdmi_audio_enable()
2095 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); in tegra_sor_hdmi_audio_enable()
2096 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960); in tegra_sor_hdmi_audio_enable()
2099 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); in tegra_sor_hdmi_audio_enable()
2100 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920); in tegra_sor_hdmi_audio_enable()
2104 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2115 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2142 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2168 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2220 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_hdmi_disable()
2287 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2293 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2298 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2302 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2309 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2316 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2328 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2351 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2359 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2366 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2370 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2374 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2375 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2380 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2388 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_hdmi_enable()
2389 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2439 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2446 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2478 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2483 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2500 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2509 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2520 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2526 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2532 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2538 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2543 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2548 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2589 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2599 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2605 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2614 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2679 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_dp_disable()
2691 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_disable()
2770 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2776 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2780 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2785 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2792 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2802 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2814 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2817 tegra_sor_writel(sor, 0, SOR_LVDS); in tegra_sor_dp_enable()
2825 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2832 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_dp_enable()
2833 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_dp_enable()
2870 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_enable()
2875 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2904 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_dp_enable()
3687 tegra_sor_writel(sor, value, SOR_INT_STATUS); in tegra_sor_irq()